Job description

Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions. We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles . About the Role Cornelis Networks builds high-performance fabric solutions for AI and HPC. We're looking for a principal-level embedded engineer to help architect firmware across our next-generation networking silicon. A key focus of the role is the management firmware that boots, secures, and controls the on-chip compute engines that accelerate collective communication (all-reduce, broadcast, reduce-scatter), alongside broader embedded architecture work across the platform. You'll own the infrastructure layer that makes these engines trustworthy and production-ready, not the collective algorithms themselves. This role is a mixture of hands-on architecture, firmware development, technical leadership, and mentorship, with heavy use of AI tools across design, implementation, and testing. Location: Remote (US) What You'll Do Architect and implement bare-metal C firmware on a RISC-V management core that provisions, boots, and supervises arrays of on-chip acceleration engines. Own the secure firmware-loading pipeline: fetch images from flash, coordinate hardware root-of-trust authentication, and distribute verified images into each engine's local memories through on-chip fan-out/DMA hardware. Build per-engine bring-up, reset sequencing, and health validation driven by control/status registers, with solid timeout and error handling and enforced security invariants. Scale firmware distribution and bring-up across many engines and multiple dies, including runtime re-boot and in-field firmware updates. Define the hardware/software contract with ASIC/RTL teams using a datamodel-first workflow (e.g., SystemRDL, Kaitai, YAML → generated code). Validate firmware against functional simulators (e.g., QEMU) with automated unit and integration tests. Set architecture standards, review designs and code, and mentor engineers. Required Qualifications 10+ years of embedded/firmware engineering, with a track record of software architecture and technical leadership. Expert C (C++ a plus) and working Python. Deep experience with bare-metal firmware on constrained cores, including manually managed local memories and low level bring-up. Experience with secure boot / image authentication and hardware root-of-trust integration. Experience programming hardware CSRs and co-designing register-level interfaces with silicon teams. Demonstrated, hands-on AI-assisted engineering proficiency, plus the judgment to validate what the AI produces. Preferred Qualifications RISC-V firmware and toolchain experience. Firmware orchestration for multi-core accelerator arrays. Hardware root-of-trust ecosystems (e.g., Caliptra) and SHA-2/signature verification. Code-generation toolchains (SystemRDL, Kaitai, CMake) and simulator-based co-verification. Familiarity with emerging AI/HPC interconnect standards: Ultra Ethernet (UEC), UALink, and ESUN. Background in HPC/AI networking, RDMA, or libfabric. Location: Remote: This role fully supports remote work for employees residing within the United States. We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry. At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives. In addition to your base pay, you’ll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match , and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave. Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Requirements

Must-haves

This role is a mixture of hands-on architecture, firmware development, technical leadership, and mentorship, with heavy use of AI tools across design, implementation, and testing.
Location: Remote (US)
Architect and implement bare-metal C firmware on a RISC-V management core that provisions, boots, and supervises arrays of on-chip acceleration engines.
Own the secure firmware-loading pipeline: fetch images from flash, coordinate hardware root-of-trust authentication, and distribute verified images into each engine's local memories through on-chip fan-out/DMA hardware.
Build per-engine bring-up, reset sequencing, and health validation driven by control/status registers, with solid
timeout and error handling and enforced security invariants.
Scale firmware distribution and bring-up across many engines and multiple dies, including runtime re-boot and in-field firmware updates.
Define the hardware/software contract with ASIC/RTL teams using a datamodel-first workflow (e.g., SystemRDL, Kaitai, YAML → generated code).
Validate firmware against functional simulators (e.g., QEMU) with automated unit and integration tests.
Set architecture standards, review designs and code, and mentor engineers.
10+ years of embedded/firmware engineering, with a track record of software architecture and technical leadership.
Deep experience with bare-metal firmware on constrained cores, including manually managed local memories and low level bring-up.
Experience with secure boot / image authentication and hardware root-of-trust integration.
Experience programming hardware CSRs and co-designing register-level interfaces with silicon teams.
Demonstrated, hands-on AI-assisted engineering proficiency, plus the judgment to validate what the AI produces.
Remote: This role fully supports remote work for employees residing within the United States.
Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks

Nice-to-haves

Expert C (C++ a plus) and working Python.
RISC-V firmware and toolchain experience.
Firmware orchestration for multi-core accelerator arrays.
Hardware root-of-trust ecosystems (e.g., Caliptra) and SHA-2/signature verification.
Code-generation toolchains (SystemRDL, Kaitai, CMake) and simulator-based co-verification.
Familiarity with emerging AI/HPC interconnect standards: Ultra Ethernet (UEC), UALink, and ESUN.
Background in HPC/AI networking, RDMA, or libfabric.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aipython

Platform: bamboohr
Effort: medium

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)

Paid Time Off