Job description

About the role Drive the cross-functional execution of our AI accelerator hardware program — owning the schedules, dependencies, and risk across silicon, board/system hardware, and the low-level software that brings it to life, from architecture through tapeout, bring-up, and scale-out. [+] You're technical enough to go a level deeper than a typical PM: comfortable in the systems-programming layer (firmware, drivers, bring-up software) where hardware and software meet, not just tracking it from the outside. What you'll do Own end-to-end program management for major hardware workstreams — schedule, dependencies, critical path, and risk from architecture through tapeout and silicon bring-up Drive cross-functional execution across silicon (design, DV, physical design, packaging), board/system hardware, and software teams; align milestones and clear dependencies Bridge hardware and the systems-software stack, coordinate (and where useful, hands-on contribute to) firmware, device drivers, and bring-up software that exercises new silicon and boards Run the program operating cadence. Planning, milestone tracking, status, risk reviews, and crisp executive communication Identify critical-path risks and drive them to resolution before they slip the schedule; own tapeout readiness and milestone gating Translate low-level technical blockers (bring-up failures, driver/firmware issues, HW/SW integration bugs) into program decisions, and help the team triage them rather than waiting on a single owner Build lightweight tracking and process that scales with the team without slowing engineers down What we're looking for 5+ years of technical program/project management in hardware, silicon, or deeply technical software, driving complex cross-functional programs to delivery Strong technical fluency — you can hold your own with chip-design and software engineers and understand the dependencies between RTL/PD/DV/packaging and compiler/runtime/bring-up Systems-programming background: hands-on C/C++ (and/or Rust), Linux internals, firmware, device drivers, or bring-up software — enough to read the code, dig into low-level issues, and earn engineers' trust Demonstrated ownership of schedule, critical path, and risk on a large multi-team program, ideally through a silicon tapeout or a comparable hardware milestone. Excellent communication and stakeholder management, from IC engineers to executives Comfort operating in ambiguity at startup pace; bias to action; lightweight, high-trust process (Optional) Silicon program experience through tapeout/bring-up; ASIC/SoC development lifecycle; hardware/software co-development; Jira/Confluence; PMP or Agile; AI/ML or accelerator domain Compensation Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO. Visa Sponsorship DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status. Export Controls Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview. Equal Opportunity DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request. Full compensation packages are based on candidate experience and relevant certifications. California pay range $129,000 — $300,000 USD Compensation Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO. Visa Sponsorship DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status. Export Controls Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview. Equal Opportunity DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.

Requirements

Must-haves

Own end-to-end program management for major hardware workstreams — schedule, dependencies, critical path, and risk from architecture through tapeout and silicon bring-up
Drive cross-functional execution across silicon (design, DV, physical design, packaging), board/system hardware, and software teams; align milestones and clear dependencies
Bridge hardware and the systems-software stack, coordinate (and where useful, hands-on contribute to) firmware, device drivers, and bring-up software that exercises new silicon and boards
Run the program operating cadence. Planning, milestone tracking, status, risk reviews, and crisp executive communication
Identify critical-path risks and drive them to resolution before they slip the schedule; own tapeout readiness and milestone gating
Translate low-level technical blockers (bring-up failures, driver/firmware issues, HW/SW integration bugs) into program decisions, and help the team triage them rather than waiting on a single owner
Build lightweight tracking and process that scales with the team without slowing engineers down
5+ years of technical program/project management in hardware, silicon, or deeply technical software, driving complex cross-functional programs to delivery
Strong technical fluency — you can hold your own with chip-design and software engineers and understand the dependencies between RTL/PD/DV/packaging and compiler/runtime/bring-up
Systems-programming background: hands-on C/C++ (and/or Rust), Linux internals, firmware, device drivers, or bring-up software — enough to read the code, dig into low-level issues, and earn engineers' trust
Demonstrated ownership of schedule, critical path, and risk on a large multi-team program, ideally through a silicon tapeout or a comparable hardware milestone.
Excellent communication and stakeholder management, from IC engineers to executives
Comfort operating in ambiguity at startup pace; bias to action; lightweight, high-trust process
(Optional) Silicon program experience through tapeout/bring-up; ASIC/SoC development lifecycle; hardware/software co-development; Jira/Confluence; PMP or Agile; AI/ML or accelerator domain

Nice-to-haves

None flagged.

Application prep

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Keywords to mirror

aigorustjiraagileml

Platform: greenhouse
Effort: quick

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)

Pto