Job description

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a key CAD member of Marvell Central Engineering, you will play a leading role in developing next-generation Multi-die 3DIC Methodology, plus CAD flow automation and tool support. You will have the opportunity to use your extensive design and CAD knowledge to define the whole organization's methodology and workflow. What You Can Expect Develop and maintain next-gen CAD Flows & Methodologies for Multi-die and Power to address the needs of Marvell s various Business Units. Contribute to the deployment, support, and regressions of these flows. Collaborate with Infrastructure teams to ensure optimal flow integration within the larger CAD framework. Drive weekly engagement with external partners and internal customers to track product requirements and EDA tool development. Display strong analytical and problem-solving skills. Participate in industry events and follow industry trends. Demonstrate a constant interest in new ideas and new learning, potentially beyond the topics described above. What We re Looking For BS/MS in EE/CS with 7 years of hands-on experience in physical design and flow development in an ASIC rtl-to-gds environment Strong proficiency in TCL and python scripting for CAD flow development Comfortable working in an agile environment with constant learning and innovation · Strong verbal and written communication skills · Experience with multi-die topics: o 2.5D/3D/3.5D die-stacking, floor planning, SOIC hybrid bonding o Inter-die extraction, multi-die analysis (IR, STA, thermal) o Advanced packaging technologies: CoWoS, EMIB, PIVR, COUPE o Interposer routing for silicon & fanout, SI/PI analysis · Experience with industry design tools o 3DIC Compiler, Integrity 3DIC, Fusion Compiler, Innovus Expected Base Pay Range (USD) 127,630 - 191,200, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps marvell.com . Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SA1

Requirements

Must-haves

o 2.5D/3D/3.5D die-stacking, floor planning, SOIC hybrid bonding
o Inter-die extraction, multi-die analysis (IR, STA, thermal)
o Advanced packaging technologies: CoWoS, EMIB, PIVR, COUPE
o Interposer routing for silicon & fanout, SI/PI analysis ·
Experience with industry design tools
o 3DIC Compiler, Integrity 3DIC, Fusion Compiler, Innovus
127,630 - 191,200, $ per annum
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps marvell.com .
Interview Integrity

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aipythonagile

Platform: workday
Effort: long