Senior Analog EDA/CAD ASIC Engineer at Nokia

Job description

High-Speed Analog EDA/CAD Engineer: Brief Description: Full-time position. Infinera is seeking an EDA/CAD Engineer to support SiGE and CMOS research & development and chip design in the Optical Modules Group (OMG) located in Sunnyvale, CA. Description: Infinera is seeking an EDA/CAD Engineer to support and develop SiGe and CMOS design solutions for the high speed analog ASIC design team. The engineer will be hands-on with all phases of tool flow including foundry interface, PDK installation and support, tool evaluation and installation, layout, archive and tapeout. The engineer must be an expert in analog and mixed-signal circuit design flows and tools. Tasks will include significant tool and PDK customization and design team support. The self-motivated engineer must be able to anticipate problems and devise effective solutions. Responsibilities: • Install, customize and support external vendor PDK’s for both SiGe and CMOS processes • Install, customize and support Custom IC and RF CAD environment for the design of high-speed (10–40 Gb/s), broad-band, mixed-signal, integrated circuits for fiber-based wireline applications. • Lead and contribute to the development of design standards, IC development processes, CAD tools and design flows. • Execute and support layout efforts including archive and tapeout processes Minimum Expertise Requirements: • Expert in high-speed analog and mixed-signal IC design concepts and must demonstrate superior critical thinking skills, problem solving capabilities and engineering judgment. • Fluent with analog EDA front and back end tools • Cadence Virtuoso, ADE • Strong SKILL programming a must • Mentor Calibre (end user support and rule deck writing) • Detailed understanding of advanced high-speed analog & mixed-signal layout concepts • FlexLM license management • Strong UNIX/Linux knowledge • Not required but preferred • Perforce • Ocean scripting and advanced modelling and simulation knowledge • Linux OS support Minimum Experience Requirements: • 5 years of experience working as a high-speed analog & mixed signal IC CAD professional is required • IC Technologies: High-speed IC technologies, including CMOS and bipolar. • IC Design Software: • Experience with configuring, documenting, and maintaining high speed analog IC design flows is a must. • Experience with transistor-level IC design and verification software, e.g. Cadence Composer, Cadence Virtuoso, Cadence Spectre, Virtuoso AMS, Mentor Calibre, Skill language, is a must. • General understanding of digital physical design flows, e.g. RTL coding, place and route, DRC/LVS verification. • Work Environment: Comfortable working in a fast-paced environment. Must be strong individual contributor, and also able to work as member of a small team. Must be able to support EPDA users and solve problems efficiently, effectively and rapidly. Education Requirements: • BS 5+ years • MS 4+ years • PhD 3+ years • Install, customize and support external vendor PDK’s for both SiGe and CMOS processes • Install, customize and support Custom IC and RF CAD environment for the design of high-speed (10–40 Gb/s), broad-band, mixed-signal, integrated circuits for fiber-based wireline applications. • Lead and contribute to the development of design standards, IC development processes, CAD tools and design flows. • Execute and support layout efforts including archive and tapeout processes • 5 years of experience working as a high-speed analog & mixed signal IC CAD professional is required • IC Technologies: High-speed IC technologies, including CMOS and bipolar. • IC Design Software: • Experience with configuring, documenting, and maintaining high speed analog IC design flows is a must. • Experience with transistor-level IC design and verification software, e.g. Cadence Composer, Cadence Virtuoso, Cadence Spectre, Virtuoso AMS, Mentor Calibre, Skill language, is a must. • General understanding of digital physical design flows, e.g. RTL coding, place and route, DRC/LVS verification. • Work Environment: Comfortable working in a fast-paced environment. Must be strong individual contributor, and also able to work as member of a small team. Must be able to support EPDA users and solve problems efficiently, effectively and rapidly. Sr EDA Cad Engineer to support analog high speed ASIC design

Requirements

Must-haves

Brief Description: Full-time position.
Infinera is seeking an EDA/CAD Engineer to support SiGE and CMOS research & development and chip design in the Optical Modules Group (OMG) located in Sunnyvale, CA.
Install, customize and support external vendor PDK’s for both SiGe and CMOS processes
Install, customize and support Custom IC and RF CAD environment for the design of high-speed (10–40 Gb/s), broad-band, mixed-signal, integrated circuits for fiber-based wireline applications.
Lead and contribute to the development of design standards, IC development processes, CAD tools and design flows.
Execute and support layout efforts including archive and tapeout processes
Expert in high-speed analog and mixed-signal IC design concepts and must demonstrate superior critical thinking skills, problem solving capabilities and engineering judgment.
Fluent with analog EDA front and back end tools
Cadence Virtuoso, ADE
Strong SKILL programming a must
Mentor Calibre (end user support and rule deck writing)
Detailed understanding of advanced high-speed analog & mixed-signal layout concepts
FlexLM license management
Strong UNIX/Linux knowledge
Ocean scripting and advanced modelling and simulation knowledge
Linux OS support
5 years of experience working as a high-speed analog & mixed signal IC CAD professional is required
IC Technologies: High-speed IC technologies, including CMOS and bipolar.
Experience with configuring, documenting, and maintaining high speed analog IC design flows is a must.
Experience with transistor-level IC design and verification software, e.g. Cadence Composer, Cadence Virtuoso, Cadence Spectre, Virtuoso AMS, Mentor Calibre, Skill language, is a must.
General understanding of digital physical design flows, e.g. RTL coding, place and route, DRC/LVS verification.
PhD 3+ years
Install, customize and support external vendor PDK’s for both SiGe and CMOS processes

Nice-to-haves

Not required but preferred

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: oracle-cloud
Effort: medium