Job description

Senior Principal Engineer, SoC Architect Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Role Overview We are seeking a highly experienced Senior Principal Engineer – SoC Architect to define and drive next-generation SoC architectures for high-performance semiconductor products. This role requires deep expertise in system-level architecture, high-speed I/O integration, performance optimization, scalability, and cross-functional technical leadership. The ideal candidate will play a critical role in shaping SoC platforms from concept through silicon realization, with strong emphasis on high-speed interfaces, subsystem architecture, interoperability, power/performance optimization, and architectural innovation. Key Responsibilities SoC Architecture Definition • Define end-to-end SoC architecture for complex semiconductor platforms across compute, memory, interconnect, security, and peripheral subsystems. • Drive architectural tradeoff analysis involving performance, power, area (PPA), latency, scalability, and cost. • Develop architectural specifications, subsystem partitioning, and top-level integration strategies. • Collaborate with product, software, firmware, RTL, verification, physical design, and validation teams throughout the development lifecycle. High-Speed I/O Architecture • Lead architecture and integration of high-speed interfaces including: PCIe, Ethernet, USB, SerDes, CXL/UCIe and other advanced interconnect protocols. • Define bandwidth, latency, coherency, buffering, QoS, and interoperability requirements. • Drive system-level performance modeling and interface optimization. • Partner with PHY, signal integrity, packaging, and board teams to ensure robust end-to-end solutions. System Performance & Modeling • Develop architectural models, traffic analysis, and workload characterization frameworks. • Drive power-aware architecture decisions and dynamic performance management strategies. Technical Leadership • Provide architectural leadership across multiple SoC programs and product generations. • Mentor senior engineers and influence organization-wide architectural methodologies. • Lead technical reviews, design evaluations, and architecture signoff discussions. • Drive alignment across hardware, firmware, software, and platform ecosystems. Cross-Functional Collaboration • Work closely with: Design and verification teams on implementation feasibility, Firmware/software teams on boot, drivers, and runtime optimization, Validation teams on bring-up and debug strategies and Product and business teams on roadmap alignment. • Interface with external IP vendors and ecosystem partners when required. Required Qualifications • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field. • 15+ years of experience in SoC/system architecture and semiconductor product development. • Proven expertise in large-scale SoC architecture definition and subsystem integration. • Strong understanding of High-speed I/O architectures and protocols, On-chip interconnects and coherency fabrics, Memory subsystem architecture, Performance modeling and analysis and Power/performance optimization techniques. • Experience with architecture modeling tools, simulation environments, and performance analysis methodologies. • Strong technical communication and leadership skills. Preferred Qualifications • Deep expertise in one or more high-speed I/O technologies such as PCIe Gen5/Gen6, CXL, UCIe, HBM, or advanced SerDes architectures. • Experience with heterogeneous compute architectures involving CPU, GPU, AI/ML accelerators, or DSP subsystems. • Knowledge of chiplet-based architectures and advanced packaging technologies. • Experience with silicon bring-up, post-silicon debug, and system validation. • Familiarity with automotive, AI/ML, datacenter, networking, or mobile SoC platforms. • Publications, patents, or industry contributions in SoC or high-speed interconnect architecture are a plus. Leadership Expectations • Influence long-term SoC technology and platform strategy. • Drive innovation in scalable and reusable architecture frameworks. • Champion engineering excellence, design quality, and execution rigor. • Foster collaboration across globally distributed engineering organizations. Salary range: $250,000 - $304,000 NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers. Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.

Requirements

Must-haves

Senior Principal Engineer, SoC Architect
Location: San Jose (on-site)
SoC Architecture Definition
Define end-to-end SoC architecture for complex semiconductor platforms across compute, memory, interconnect, security, and peripheral subsystems.
Drive architectural tradeoff analysis involving performance, power, area (PPA), latency, scalability, and cost.
Develop architectural specifications, subsystem partitioning, and top-level integration strategies.
Collaborate with product, software, firmware, RTL, verification, physical design, and validation teams throughout the development lifecycle.
High-Speed I/O Architecture
Lead architecture and integration of high-speed interfaces including: PCIe, Ethernet, USB, SerDes, CXL/UCIe and other advanced interconnect protocols.
Define bandwidth, latency, coherency, buffering, QoS, and interoperability requirements.
Drive system-level performance modeling and interface optimization.
Partner with PHY, signal integrity, packaging, and board teams to ensure robust end-to-end solutions.
System Performance & Modeling

Nice-to-haves

Deep expertise in one or more high-speed I/O technologies such as PCIe Gen5/Gen6, CXL, UCIe, HBM, or advanced SerDes architectures.
Experience with heterogeneous compute architectures involving CPU, GPU, AI/ML accelerators, or DSP subsystems.
Knowledge of chiplet-based architectures and advanced packaging technologies.
Experience with silicon bring-up, post-silicon debug, and system validation.
Familiarity with automotive, AI/ML, datacenter, networking, or mobile SoC platforms.
Publications, patents, or industry contributions in SoC or high-speed interconnect architecture are a plus.
Leadership Expectations
Influence long-term SoC technology and platform strategy.
Drive innovation in scalable and reusable architecture frameworks.
Champion engineering excellence, design quality, and execution rigor.
Foster collaboration across globally distributed engineering organizations.

Application prep

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aiml

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