Job description

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of advanced-node physical design, where a 50ps timing violation at 3nm is not an abstraction but a problem you own and solve before tapeout . The difference between a chip that works and one that doesn't often comes down to decisions you made during floorplanning or a clock-tree strategy you refined three months before signoff, and you have learned to see those moments coming. You think in flows, not just tools. When you open ICC2 or Fusion Compiler, you are not just running commands, you are building repeatable methodologies that make the next block faster, cleaner, and more predictable. Automation is not a nice-to-have for you, it is how you scale your impact across a team working on subsystems that will ship in products used by millions. Timing closure does not scare you. Neither does working with a distributed team across time zones to debug a setup violation that only shows up in one corner. You ask the right questions, you dig into the data, and you do not stop until the path is clean and the methodology is documented. At Synopsys, you will work on real silicon at the bleeding edge, with tools you already know and problems that actually matter. What You'll Be Doing • Drive timing closure and signoff readiness for advanced-node designs at 5nm, 3nm, and below, working across block, subsystem, and full-chip implementations • Develop and refine physical design methodologies and automation flows using TCL, Python, and Perl to improve design quality, turnaround time, and predictability • Perform static timing analysis, clock-tree synthesis, and ECO implementation using PrimeTime , ICC2, Fusion Compiler, and industry-standard signoff tools • Analyze design data and PPA trends to identify bottlenecks, optimize workflows, and inform next-generation flow development • Collaborate with cross-functional teams including front-end design, verification, and CAD to ensure successful silicon delivery on schedule • Contribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to improve implementation outcomes • Troubleshoot complex physical design challenges including congestion, power integrity, and multi-corner timing convergence, developing scalable technical solutions that can be reused across projects The Impact You Will Have • Enable faster time-to- tapeout for advanced-node designs by building automation and methodologies that reduce manual intervention and improve first-pass success rates • Improve PPA outcomes across multiple projects by identifying design patterns, bottlenecks, and optimization opportunities that inform both current and future implementations • Strengthen signoff predictability and reduce late-stage ECOs by establishing robust timing closure flows and early analysis checkpoints • Scale physical design expertise across the organization by creating reusable flows, documentation, and best practices that other engineers can adopt • Contribute to the evolution of AI-driven design tools and methodologies that will shape how Synopsys and its customers approach next-generation semiconductor development • Support successful silicon bring-up and customer deployments by ensuring designs meet all timing, power, and area targets with margin • Influence tool development and roadmap priorities by providing real-world feedback from advanced-node implementations to internal CAD and product teams What You'll Need • Bachelor's or Master's degree in Electrical Engineering , Computer Engineering, or a related technical field • 8+ years of hands-on experience in ASIC physical design, implementation, and timing closure across block, subsystem, or chip-level environments • Deep expertise with industry-standard implementation tools including Synopsys ICC2, Fusion Compiler, or Cadence Innovus • Strong working knowledge of timing, power, and signoff tools such as PrimeTime , PrimeTime PX, PrimeShield , RedHawk, Formality, or Conformal • Proven ability to develop design flows, methodologies, and productivity-enhancing automation using TCL, Python, Perl, or similar scripting languages • Experience with advanced-node semiconductor design at 7nm or below, including leading-edge process technologies and associated design challenges • Exposure to machine learning, AI-assisted design optimization, or data-driven engineering workflows is a strong plus Who You Are • You can walk into a timing review with 500 failing paths and walk out with a prioritized plan that gets the design to signoff without heroics • You do not wait for someone to tell you the flow is broken, you see the pattern in the data, write the script, and fix it before it becomes everyone's problem • You are comfortable explaining a complex clock-tree tradeoff to a design lead in two sentences without losing the technical nuance or oversimplifying the risk • You work well across a global team, coordinating with engineers in multiple time zones and adapting your communication style to get alignment without endless meetings • You are an excellent problem solver who does not need perfect documentation to get started, you dig into the tools, read the logs, and figure it out • You are self-motivated and independent, able to own a block or subsystem implementation from floorplan through signoff with minimal hand-holding The Team You'll Be Part Of Your recruiter will share more about the team structure and mission during the interview process. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

Requirements

Must-haves

At Synopsys, you will work on real silicon at the bleeding edge, with tools you already know and problems that actually matter.
What You'll Be Doing
Drive timing closure and signoff readiness for advanced-node designs at 5nm, 3nm, and below, working across block, subsystem, and full-chip implementations
Develop and refine physical design methodologies and automation flows using TCL, Python, and Perl to improve design quality, turnaround time, and predictability
Perform static timing analysis, clock-tree synthesis, and ECO implementation using PrimeTime , ICC2, Fusion Compiler, and industry-standard signoff tools
Analyze design data and PPA trends to identify bottlenecks, optimize workflows, and inform next-generation flow development
Collaborate with cross-functional teams including front-end design, verification, and CAD to ensure successful silicon delivery on schedule
Contribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to improve implementation outcomes
Troubleshoot complex physical design challenges including congestion, power integrity, and multi-corner timing convergence, developing scalable technical solutions that can be reused across projects
The Impact You Will Have
Enable faster time-to- tapeout for advanced-node designs by building automation and methodologies that reduce manual intervention and improve first-pass success rates
Improve PPA outcomes across multiple projects by identifying design patterns, bottlenecks, and optimization opportunities that inform both current and future implementations
Strengthen signoff predictability and reduce late-stage ECOs by establishing robust timing closure flows and early analysis checkpoints
Scale physical design expertise across the organization by creating reusable flows, documentation, and best practices that other engineers can adopt
Contribute to the evolution of AI-driven design tools and methodologies that will shape how Synopsys and its customers approach next-generation semiconductor development
Support successful silicon bring-up and customer deployments by ensuring designs meet all timing, power, and area targets with margin
Influence tool development and roadmap priorities by providing real-world feedback from advanced-node implementations to internal CAD and product teams
What You'll Need
Bachelor's or Master's degree in Electrical Engineering , Computer Engineering, or a related technical field
8+ years of hands-on experience in ASIC physical design, implementation, and timing closure across block, subsystem, or chip-level environments
Deep expertise with industry-standard implementation tools including Synopsys ICC2, Fusion Compiler, or Cadence Innovus
Strong working knowledge of timing, power, and signoff tools such as PrimeTime , PrimeTime PX, PrimeShield , RedHawk, Formality, or Conformal
Proven ability to develop design flows, methodologies, and productivity-enhancing automation using TCL, Python, Perl, or similar scripting languages
Experience with advanced-node semiconductor design at 7nm or below, including leading-edge process technologies and associated design challenges

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aipythonmachine learning

Platform: avature
Effort: medium

Benefits

Benefits detected in the listing.

Wellness