Job description

Junior Member of Technical Staff - AI Silicon Digital Design Engineer About Unconventional Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand for computation - a demand that is now fundamentally limited by energy, not just in the datacenter, but at a global scale. At Unconventional, our mission is to solve this. We are rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient. We're doing this by exploiting the rich physics of semiconductors, mapping neural networks directly to the device physics rather than relying on layers of inefficient abstraction. The Role As a Member of Technical Staff, SOC Design Engineer, you will be a foundational member of our small, multi-disciplinary R&D team. We are looking for accomplished and highly motivated individuals with a strong understanding of SOC design who are excited to tackle the hardest, most ambiguous technical challenges at the intersection of AI, physics, and computer architecture. You will be responsible for driving invention, prototyping, and validation of the core components of our novel computing platform. Responsibilities SoC Design & Integration: Contribute to the micro-architecture definition and integration of digital blocks, including CPU, interfaces and memory subsystems. Assist in the integration of third-party IP into the main SoC fabric. Hands-on RTL Implementation: Write clean, synthesizable, and high-performance Verilog/SystemVerilog code. Perform hands-on RTL design for SoC blocks and digital interfaces, focusing on meeting power, performance, and area (PPA) targets. Implement and debug key digital interfaces to ensure system stability. Implement advanced techniques for low-power design (clock gating, power domains) Synthesis & Timing : Perform initial synthesis and formal verification (LEC) to ensure the design is routable and meets frequency targets. Create block-level timing constraints Lint & CDC: Run and resolve RTL linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks using industry standard tools. Design Verification (DV) Support: Participate in the block-level verification plan and help develop a robust verification environment. Triage and debug simulation failures to ensure functional correctness. External Coordination: Support created technical interfaces, and assist in the hand-off between internal design and physical implementation teams. Minimum Qualifications Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field. Experience: 4+ years of industry experience in digital ASIC/SoC design Strong Technical Expertise: Expertise in Verilog RTL coding and digital design fundamentals. Design Flow Proficiency: Familiarity with standard EDA tools for simulation, assertions, synthesis, linting, and clock domain crossing (CDC) analysis Understanding of the full ASIC design flow, from specification to tape-out. Communication: Excellent written and verbal communication skills Preferred Qualifications (Nice to Have) Experience with design constraints or architectures related to Machine Learning/Neural Network accelerators is a strong plus. Experience with UVM (Universal Verification Methodology) environments for basic debugging. Knowledge of formal verification techniques. Exposure to post-silicon bring-up and lab debugging using logic analyzers or oscilloscopes. Experience with modern design methods, including generative AI code development platforms. Experience integrating large analog mixed-signal blocks into larger subsystems. Why Join Us? The Mission: Tackle a fundamental problem that could redefine computing for the next 50 years. The Impact: Be a foundational member of a world-class team with an outsized opportunity for ownership and impact. The Challenge: Work on deeply challenging, intellectually stimulating problems that sit at the cutting edge of multiple fields. The Perks: A comprehensive package including best-in-class health benefits, 401k matching, truly unlimited PTO, and complimentary meals in our Palo Alto office.

Requirements

Must-haves

Junior Member of Technical Staff - AI Silicon Digital Design Engineer
Contribute to the micro-architecture definition and integration of digital blocks, including CPU, interfaces and memory subsystems.
Assist in the integration of third-party IP into the main SoC fabric.
Write clean, synthesizable, and high-performance Verilog/SystemVerilog code.
Perform hands-on RTL design for SoC blocks and digital interfaces, focusing on meeting power, performance, and area (PPA) targets.
Implement and debug key digital interfaces to ensure system stability.
Implement advanced techniques for low-power design (clock gating, power domains)
Perform initial synthesis and formal verification (LEC) to ensure the design is routable and meets frequency targets.
Create block-level timing constraints
Lint & CDC: Run and resolve RTL linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks using industry standard tools.
Participate in the block-level verification plan and help develop a robust verification environment.
Triage and debug simulation failures to ensure functional correctness.
Support created technical interfaces, and assist in the hand-off between internal design and physical implementation teams.
Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
Experience: 4+ years of industry experience in digital ASIC/SoC design
Expertise in Verilog RTL coding and digital design fundamentals.
Familiarity with standard EDA tools for simulation, assertions, synthesis, linting, and clock domain crossing (CDC) analysis
Understanding of the full ASIC design flow, from specification to tape-out.
Communication: Excellent written and verbal communication skills
Experience with design constraints or architectures related to Machine Learning/Neural Network accelerators is a strong plus.
Experience with UVM (Universal Verification Methodology) environments for basic debugging.
Knowledge of formal verification techniques.
Exposure to post-silicon bring-up and lab debugging using logic analyzers or oscilloscopes.

Nice-to-haves

Preferred Qualifications (Nice to Have)

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Keywords to mirror

aimachine learning

Platform: greenhouse
Effort: quick

Benefits

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401k

Pto