Ph.D. Intern - Analog, Mixed Signal & Circuit Design
Marvell· enterprise· Semiconductors· Sep 4, 2026 · 2mo ago
Santa Clara CA
In office
Internship
Intern
$53K–$100K est.
Job description
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Every time a hyperscaler trains a frontier AI model, streams a zettabyte of data across a data center fabric, or pushes a coherent optical signal across a transoceanic link, analog and mixed-signal circuits are doing the work that makes it possible. At Marvell, our analog design team is the reason those circuits exist. The custom XPUs, the 224G and 448G SerDes IP, the Silicon Photonics light engines, the co-packaged optics platforms powering the world's largest AI infrastructure — none of it ships without the analog IP this team designs from scratch. This is one of the few places in the industry where analog engineers work at the true physical limit of what silicon can do, on problems at and beyond 448G that have no established design playbook and no known solutions — open research questions that require exactly the kind of rigorous, first-principles thinking a Ph.D. program is built to develop.
Our Ph.D. Intern Program embeds doctoral candidates directly inside active design teams, working alongside staff and distinguished engineers on production IP and research-stage silicon. Projects are selected because they sit at the intersection of Marvell's most pressing engineering challenges and the circuit theory, device physics, and signal processing that define doctoral research in electrical engineering. Interns work through the complete design flow and participate in a structured analog design curriculum alongside their peers. What you will take away from this program is something no coursework can replicate: the experience of seeing your own research become real, working silicon, deployed at scale inside the world's most advanced AI infrastructure.
What You Can Expect
As our Ph.D. Analog Design Intern, every day you will work on circuit design problems tied directly to your doctoral research focus. Specifically, you can expect to:
Design, simulate, and verify analog and mixed-signal circuit blocks across the full design flow — from architecture and schematic through simulation, layout coordination, and silicon bring-up
Work on production-grade IP including high-speed SerDes building blocks, Silicon Photonics driver and receiver circuits, ADC/DAC architectures, PLLs, clock distribution networks, LDOs, and other precision analog circuits in advanced CMOS FinFET processes
Use industry-standard tools including Cadence and MATLAB throughout your project
Collaborate directly with layout engineers to implement your designs and iterate based on simulation and silicon feedback
Attend and contribute to design reviews alongside the full engineering team
Present your work — both the research framing and the design results — to the engineers around you
Participate in a structured analog design curriculum alongside your Ph.D. intern peers
What We re Looking For
To thrive in this role, you must have experience designing analog and mixed-signal circuits at the transistor level. Specifically:
Currently enrolled in a Ph.D. program in Electrical Engineering or a related field, with a research focus in analog, mixed-signal, or RF circuit design
Demonstrate hands-on experience designing and simulating analog circuit blocks such as PLLs, SerDes building blocks, ADCs, DACs, LDOs, amplifiers, or high-speed I/O — not just theoretical familiarity
Apply strong fundamentals in transistor-level circuit design, including device physics, noise analysis, linearity, stability, and low-power techniques in advanced CMOS processes
Simulate and verify designs independently using industry-standard tools such as Cadence Virtuoso and Spectre; experience with MATLAB or Python for system-level modeling is a plus
Communicate design decisions and tradeoffs clearly — you will be expected to present your work to the engineering team and defend your approach
Preferred Qualifications
Experience designing in FinFET process nodes (7nm, 5nm, 3nm, or equivalent)
Familiarity with high-speed serial link architectures, optical transceiver circuits, or Die-to-Die interconnect design
Exposure to layout-aware design, parasitic extraction, or post-layout simulation
Experience with behavioral modeling in Verilog-A or similar
Expected Base Pay Range (USD)
38 - 76, $ per hour.
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success. Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights for our interns: medical, dental, and vision coverage, perks and discounts, robust mental health resources to prioritize emotional well-being, and paid holidays. Additional compensation may be available for intern PhD candidates. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps marvell.com .
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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