Job description

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are. Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people s lives; making the world a better place, one processor at a time. Are you ready? To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages. Job Description: The Role SiFive is looking for a Senior Staff Design Verification Engineer to lead verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs. This is a Senior Staff individual-contributor role focused on defining verification strategy, identifying risk early, solving complex subsystem-level problems, and raising the quality bar across the broader verification effort. In this role, you will work across architecture, RTL, formal, and design verification teams to verify coherent data movement, protocol correctness, ordering, flow control, quality-of-service behavior, and subsystem integration across multiple interfaces and bridge paths. Responsibilities Own verification planning and execution for a scalable cache-coherent interconnect subsystem, from block-level verification through subsystem integration and signoff. Define verification strategy, test plans, environments, and closure criteria for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, QoS, and error handling. Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models to validate complex interconnect and protocol behavior. Drive verification of subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths, including CHI, ACE, CXL, and related coherent interconnect flows. Create high-value directed and constrained-random scenarios that expose corner cases in coherency, concurrency, credits, arbitration, QoS, and bandwidth-sensitive behavior. Partner closely with architecture, RTL, formal, and software teams to review specifications, close ambiguities early, and improve overall verification quality. Debug failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content. Contribute to methodology and infrastructure improvements that benefit the broader horizontal interconnect verification effort, not just the block directly assigned to you. Mentor engineers and help raise verification quality across the team. Minimum Qualifications BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 8 years of experience in ASIC or SoC design verification, with depth appropriate for a Senior Staff / T5 role. Strong hands-on experience with SystemVerilog and building reusable verification infrastructure for complex hardware subsystems. Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior, and verification of ordering and flow-control semantics. Strong protocol knowledge in CHI, ACE, CXL, AXI, or similar coherent and high-performance interconnect standards. Experience creating test plans, assertions, coverage models, and debug workflows for complex hardware subsystems. Strong scripting and automation skills in Python or similar languages. Strong communication skills and the ability to work effectively across architecture, RTL, and verification teams in a fast-moving environment. Preferred Qualifications Experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance SoCs. Experience with protocol-conversion or bridge-heavy subsystems. Experience with formal verification, performance-oriented verification, or emulation / FPGA-assisted debug. Demonstrated technical leadership and the ability to influence verification quality beyond immediate ownership. What Success Looks Like Verification plans are complete, concrete, and aligned to the real architectural risks. Critical bugs are found early, reproduced efficiently, and closed with durable fixes. Coverage and test quality improve meaningfully under your ownership. The coherent interconnect verification effort becomes more scalable, predictable, and reusable because of your contributions. Design and architecture teams rely on you as a strong technical partner for difficult verification and debug problems. You will be part of a high performance Out-of-Order Core team that focuses on verification of components such as Frontend, Mid-Core, Load-Store Unit, Integer and Floating Execution Unit, as well as Vector Unit that implement the latest RVV. BS/MS Degree in EE, CE or CS 8 years relevant experience with IP/Component functional verification, preferably in Core/CPU verification Deep understand of computer architecture is desired Seasoned developer using object oriented programing principles In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! Additional Information: This position requires a successful background and reference checks and satisfactory proof of your right to work in United States of America Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals. SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.

Requirements

Must-haves

The Role SiFive is looking for a Senior Staff Design Verification Engineer to lead verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs.
Responsibilities Own verification planning and execution for a scalable cache-coherent interconnect subsystem, from block-level verification through subsystem integration and signoff.
Define verification strategy, test plans, environments, and closure criteria for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, QoS, and error handling.
Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models to validate complex interconnect and protocol behavior.
Drive verification of subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths, including CHI, ACE, CXL, and related coherent interconnect flows.
Create high-value directed and constrained-random scenarios that expose corner cases in coherency, concurrency, credits, arbitration, QoS, and bandwidth-sensitive behavior.
Partner closely with architecture, RTL, formal, and software teams to review specifications, close ambiguities early, and improve overall verification quality.
Debug failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
Contribute to methodology and infrastructure improvements that benefit the broader horizontal interconnect verification effort, not just the block directly assigned to you.
Mentor engineers and help raise verification quality across the team.
Minimum Qualifications BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
8 years of experience in ASIC or SoC design verification, with depth appropriate for a Senior Staff / T5 role.
Strong hands-on experience with SystemVerilog and building reusable verification infrastructure for complex hardware subsystems.
Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior, and verification of ordering and flow-control semantics.
Strong protocol knowledge in CHI, ACE, CXL, AXI, or similar coherent and high-performance interconnect standards.
Experience creating test plans, assertions, coverage models, and debug workflows for complex hardware subsystems.
Strong scripting and automation skills in Python or similar languages.
Strong communication skills and the ability to work effectively across architecture, RTL, and verification teams in a fast-moving environment.
Experience with protocol-conversion or bridge-heavy subsystems.
Experience with formal verification, performance-oriented verification, or emulation / FPGA-assisted debug.
Demonstrated technical leadership and the ability to influence verification quality beyond immediate ownership.
What Success Looks Like Verification plans are complete, concrete, and aligned to the real architectural risks.
Critical bugs are found early, reproduced efficiently, and closed with durable fixes.

Nice-to-haves

Preferred Qualifications Experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance SoCs.

Application prep

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Keywords to mirror

machine learningpython

Platform: workday
Effort: long

Benefits

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Paid Time Off