Job description

About the role Own the board-level physical design that turns our accelerator silicon into systems. You'll take high-speed, high-power designs from placement through fabrication release — defining stackups, escaping large fine-pitch BGAs, routing multi-hundred-amp power delivery, and holding the constraint discipline that lets a channel close margin in the lab and not just in simulation. You'll work at the seam where the package meets the system, partnering with signal and power integrity, packaging, and hardware systems, and directly with the fabrication and assembly partners who build what you release. When a board comes back and something doesn't behave, you're one of the people who knows why. What will you do Own board-level physical design for the systems our AI accelerators ship in stackup and impedance definition, placement, high-speed routing, and fabrication and assembly release packages Own high-current power delivery layout and large fine-pitch BGA escape for advanced accelerator packages Drive DFM/DFA with PCB fabrication and contract manufacturing partners, and support board bring-up and debug Use and develop AI assisted tool flows to accelerate layout, review, and design-rule checking What we're looking for Exceptional abilities in constraint-driven layout of complex high-speed, high-current boards: controlled impedance and stackup definition, return-path and crosstalk management, length and skew matching, and via optimization 8+ years of PCB layout experience on server, networking, or accelerator-class systems at high layer counts Hands-on with industry-standard layout tools (Cadence Allegro, Siemens Xpedition, Altium, or equivalent) and release formats (Gerber, ODB++, IPC-2581) Demonstrated ability to work closely with signal-integrity, power-integrity, packaging, and hardware systems teams to implement and close complex constraint sets across package and board (Optional) 2.5D / 3D and multi-die package interfaces (CoWoS, EMIB, chiplets, HBM), rigid-flex or backplane design, CAD automation scripting, IPC CID / CID+, or overseas PCB fabrication and PCBA partner management Full compensation packages are based on candidate experience and relevant certifications. California pay range $150,000 — $215,000 USD Compensation Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO. Visa Sponsorship DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status. Export Controls Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview. Equal Opportunity DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.

Requirements

Must-haves

What will you do
Own board-level physical design for the systems our AI accelerators ship in stackup and impedance definition, placement, high-speed routing, and fabrication and assembly release packages
Own high-current power delivery layout and large fine-pitch BGA escape for advanced accelerator packages
Drive DFM/DFA with PCB fabrication and contract manufacturing partners, and support board bring-up and debug
Use and develop AI assisted tool flows to accelerate layout, review, and design-rule checking
8+ years of PCB layout experience on server, networking, or accelerator-class systems at high layer counts
Hands-on with industry-standard layout tools (Cadence Allegro, Siemens Xpedition, Altium, or equivalent) and release formats (Gerber, ODB++, IPC-2581)
Demonstrated ability to work closely with signal-integrity, power-integrity, packaging, and hardware systems teams to implement and close complex constraint sets across package and board
(Optional) 2.5D / 3D and multi-die package interfaces (CoWoS, EMIB, chiplets, HBM), rigid-flex or backplane design, CAD automation scripting, IPC CID / CID+, or overseas PCB fabrication and PCBA partner management
Visa Sponsorship
Export Controls
Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

Nice-to-haves

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Keywords to mirror

Platform: greenhouse
Effort: quick

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)

Pto