Senior ATE Wafer Test Engineer at Nokia

Job description

Description: • Sr Analog Wafer Level ATE Test Engineer to support existing IC ATE development and production • Experience with Analog ATE wafer sort testing and STDF data handling is required. • Knowledge of automated test equipment (ATE) platforms, probe card development, software and hardware for wafer level testing. • The candidate is expected to have hands on experience with NPI test development, WS production yield analysis and yield drop out debug and disposition. • Familiar & comfortable with high-performance medium volume ASICs, production environment • Ability to write status reports, schedules and project plans and present results in general meeting formats. • Capable to contact vendors for project schedule, testing status, booking equipment, and test debugging • Collection, analysis, correlation and interpretation of data using statistical techniques and industry standard tools is required • Some experience with scripting and simple programming skills. • Critical thinking skills to debug and solve problems required • Experienced with scheduling and planning projects with external vendors and customers • RF ATE testing experience is a plus Responsibilities: • Interface with external vendors for R&D and production testing • Ensure and correlate test SW and HW to written Test Plan • Production yield tracking, milestone tracking, problem assessment/disposition and invoice tracking • Wafer level ATE platform support of production, yield analysis, failure Paretos and yield improvement • Production logistics including ASIC wafer tracking and travelers • Supporting engineering releases through pilot runs and production • Develop, debug and release production methods and procedures to improve efficiency and yield compliant to TL/ISO manufacturing standards Experience Required: • BS EE/physics with 5+ years industrial experience • Analog wafer level IC testing • Must have experience with probe card cleaning, maintenance and debug • Must have experience with ATE platform and wafer prober setup and operation • Must be able to assemble coherent and concise reports summarizing status and next steps • Must be able to effectively present findings to a cross-functional, collaborative team environment • Prefer experience with Galaxy or JMP data analysis tools. • Prefer Advantest 93K expertise including calibration, TL/ISO compliance and ESD compliance • Prefer expertise with Perl, VB, SQL and Perforce • Prefer UNIX/Linux experience Skills Required: • Proficient interacting with design and application engineers • Strong debug and analytical skills • Self-motivated team player • Strong time and project management skills • Detail oriented with all aspects of technical work and vendor interactions Excellent verbal and written communication skills • Nokia is seeking a Sr Analog Wafer Level ATE Test Engineer to support existing IC ATE development and production • The position is within the Optical Modules Group (OMG) in Sunnyvale, CA

Requirements

Must-haves

Sr Analog Wafer Level ATE Test Engineer to support existing IC ATE development and production
Experience with Analog ATE wafer sort testing and STDF data handling is required.
Knowledge of automated test equipment (ATE) platforms, probe card development, software and hardware for wafer level testing.
The candidate is expected to have hands on experience with NPI test development, WS production yield analysis and yield drop out debug and disposition.
Familiar & comfortable with high-performance medium volume ASICs, production environment
Ability to write status reports, schedules and project plans and present results in general meeting formats.
Capable to contact vendors for project schedule, testing status, booking equipment, and test debugging
Collection, analysis, correlation and interpretation of data using statistical techniques and industry standard tools is required
Some experience with scripting and simple programming skills.
Critical thinking skills to debug and solve problems required
Experienced with scheduling and planning projects with external vendors and customers
Interface with external vendors for R&D and production testing
Ensure and correlate test SW and HW to written Test Plan
Production yield tracking, milestone tracking, problem assessment/disposition and invoice tracking
Wafer level ATE platform support of production, yield analysis, failure Paretos and yield improvement
Production logistics including ASIC wafer tracking and travelers
Supporting engineering releases through pilot runs and production
Develop, debug and release production methods and procedures to improve efficiency and yield compliant to TL/ISO manufacturing standards
BS EE/physics with 5+ years industrial experience
Analog wafer level IC testing
Must have experience with probe card cleaning, maintenance and debug
Must have experience with ATE platform and wafer prober setup and operation
Must be able to assemble coherent and concise reports summarizing status and next steps

Nice-to-haves

RF ATE testing experience is a plus

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

sql

Platform: oracle-cloud
Effort: medium