Job description

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are. Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people s lives; making the world a better place, one processor at a time. Are you ready? To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages. Job Description: About the Role SiFive is looking for a Staff Design Verification Engineer to drive verification of high-performance CPU core functionality, with primary focus on ALU and integer-execution microarchitecture. This is a Staff individual-contributor role within the CPU Design Verification organization, focused on high-performance out-of-order CPU core development. The role spans core execution areas such as ALU pipelines, issue/dispatch interactions, dependency and forwarding behavior, replay and recovery handling, exception behavior, and related midcore control interactions. We are looking for an engineer who can independently own complex verification problems, define verification strategy early, identify microarchitectural risk, and raise verification quality across the broader CPU DV effort. You will work closely with architecture, RTL, performance, and verification teams to ensure design intent is captured correctly, difficult corner cases are verified thoroughly, and signoff quality is achieved with strong technical judgment and scalable methodology. Responsibilities Own verification planning and execution for ALU- and execution-focused CPU core functionality, from block-level verification through core-level integration and signoff. Drive verification strategy, test planning, debug, coverage analysis, and closure for complex execution-pipeline behaviors and microarchitectural interactions. Define effective verification approaches for challenging ALU-related behaviors such as arithmetic and logical execution correctness, compare and branch-condition generation, operand dependency handling, bypass and forwarding behavior, replay scenarios, flush and recovery interactions, exception behavior, and issue/dispatch to execute/commit pipeline interactions. Verify corner-case interactions between ALU execution and surrounding core logic, including scoreboarding, operand readiness, structural conflicts, speculative execution effects, and interaction with branch, load/store, and commit behavior. Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency. Partner closely with architecture and design teams from early feature-definition stages to review specifications, identify ambiguity, and improve design debugability and verification completeness. Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure. Contribute reusable methodology, automation, and infrastructure that improve productivity and verification quality across future CPU core programs. Mentor other engineers through technical reviews, debugging guidance, and stronger verification practices. Minimum Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 7 years of relevant experience in ASIC, CPU/core, or SoC design verification, with strong hands-on ownership of complex verification problems appropriate for a Staff role. Strong hands-on experience with SystemVerilog-based verification and modern verification methodologies. Direct experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture. Experience verifying one or more CPU execution areas such as ALU pipelines, midcore execution/control logic, issue and dispatch behavior, dependency handling, forwarding, replay, or related integer-execution functionality. Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure. Strong debugging skills and the ability to translate architectural intent into effective verification strategy and execution. Familiarity with Python, C/C , or similar scripting/programming languages used for DV infrastructure and automation. Preferred Qualifications Direct experience with high-performance out-of-order CPU core verification. Experience verifying ALU microarchitectural behaviors such as integer arithmetic and logical operations, compare/condition evaluation, flag or condition-code generation, dependency tracking, forwarding correctness, replay, flush, and recovery behavior. Experience verifying execution-pipeline correctness across issue, operand collection, execute, writeback, and commit boundaries. Experience developing high-value assertions, checkers, and scoreboards for control-heavy, dependency-sensitive, or timing-sensitive CPU behavior. Experience using formal verification, emulation, or acceleration for high-risk or hard-to-observe verification problems. Experience collaborating effectively with performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives. Experience influencing verification methodology beyond immediate ownership scope through reusable infrastructure, automation, or technical leadership. You will be part of a high performance Out-of-Order Core team that focuses on verification of components such as Frontend, Mid-Core, Load-Store Unit, Integer and Floating Execution Unit, as well as Vector Unit that implement the latest RVV. BS/MS Degree in EE, CE or CS 5-8 years relevant experience with IP/Component functional verification, preferably in Core/CPU verification Deep understand of computer architecture is desired Experienced developer using Object Oriented Programing principles In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! Additional Information: This position requires a successful background and reference checks and satisfactory proof of your right to work in United States of America Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals. SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.

Requirements

Must-haves

SiFive is looking for a Staff Design Verification Engineer to drive verification of high-performance CPU core functionality, with primary focus on ALU and integer-execution microarchitecture.
This is a Staff individual-contributor role within the CPU Design Verification organization, focused on high-performance out-of-order CPU core development.
Responsibilities Own verification planning and execution for ALU- and execution-focused CPU core functionality, from block-level verification through core-level integration and signoff.
Drive verification strategy, test planning, debug, coverage analysis, and closure for complex execution-pipeline behaviors and microarchitectural interactions.
Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.
Partner closely with architecture and design teams from early feature-definition stages to review specifications, identify ambiguity, and improve design debugability and verification completeness.
Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
Contribute reusable methodology, automation, and infrastructure that improve productivity and verification quality across future CPU core programs.
Mentor other engineers through technical reviews, debugging guidance, and stronger verification practices.
Minimum Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
7 years of relevant experience in ASIC, CPU/core, or SoC design verification, with strong hands-on ownership of complex verification problems appropriate for a Staff role.
Strong hands-on experience with SystemVerilog-based verification and modern verification methodologies.
Direct experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture.
Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
Strong debugging skills and the ability to translate architectural intent into effective verification strategy and execution.
Familiarity with Python, C/C , or similar scripting/programming languages used for DV infrastructure and automation.
Experience verifying execution-pipeline correctness across issue, operand collection, execute, writeback, and commit boundaries.
Experience developing high-value assertions, checkers, and scoreboards for control-heavy, dependency-sensitive, or timing-sensitive CPU behavior.
Experience using formal verification, emulation, or acceleration for high-risk or hard-to-observe verification problems.
Experience collaborating effectively with performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.
Experience influencing verification methodology beyond immediate ownership scope through reusable infrastructure, automation, or technical leadership.
BS/MS Degree in EE, CE or CS
5-8 years relevant experience with IP/Component functional verification, preferably in Core/CPU verification

Nice-to-haves

Preferred Qualifications Direct experience with high-performance out-of-order CPU core verification.

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machine learningpython

Platform: workday
Effort: long

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Paid Time Off