Job description

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly experienced architect with a strong background in memory PHYs and power modeling, ready to lead innovation in efficient silicon solutions. With 15+ years in engineering and a BSEE/MSEE, you bring expertise with industry-standard tools—including Power Artist and PTPX—a collaborative spirit, and a passion for mentoring teams and delivering outstanding results. You thrive in environments where you drive power models, collaborate with PHY architects to define architecture that meet product goals, take ownership of outcomes, and work seamlessly with large cross-functional teams to ensure successful project delivery. What You’ll Be Doing: • Designing and developing power-efficient memory PHY architectures. • Driving the creation and optimization of effective power models for memory subsystems. • Taking responsibility for project outcomes and ensuring high-quality deliverables. • Utilizing tools such as Power Artist and PTPX for power analysis and optimization. • Collaborating closely with large cross-functional teams—including engineering, product management, and customers—to align requirements and integration. • Mentoring engineers and sharing best practices. • Evaluating new technologies or architectural improvements . • Supporting IP integration and validation efforts. The Impact You Will Have: • Advance Synopsys’ leadership in memory PHY innovation. • Drive efficient power modeling practices that enhance product performance and competitiveness. • Take ownership of outcomes, ensuring projects meet and exceed expectations. • Shape future technology and product direction. • Support robust, scalable architectures. • Foster a collaborative and inclusive team culture across large, multidisciplinary groups. • Deliver solutions trusted by leading semiconductor companies. What You’ll Need: • 15+ years in memory PHY architecture and power modeling. • Expertise with industry-standard design and simulation tools, including Power Artist and PTPX. • Proven experience driving efficient power models and taking responsibility for outcomes. • BSEE/MSEE required . • Strong analytical and communication skills . • Strong digital and/or analog design skills • Ability to work effectively with large cross-functional teams. Who You Are: • Strategic, collaborative, and detail-oriented . • Inclusive leader and effective communicator. • Adaptable and innovative problem-solver. • Accountable and results-driven . The Team You’ll Be A Part Of: Join a diverse, expert engineering group focused on power-optimized memory PHY IP for next-generation silicon platforms. You will collaborate with a large cross-functional team to drive innovation and ensure successful outcomes. Rewards and Benefits: We offer comprehensive health, wellness, and financial benefits. Your recruiter will provide more details during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

Requirements

Must-haves

Designing and developing power-efficient memory PHY architectures.
Driving the creation and optimization of effective power models for memory subsystems.
Taking responsibility for project outcomes and ensuring high-quality deliverables.
Utilizing tools such as Power Artist and PTPX for power analysis and optimization.
Collaborating closely with large cross-functional teams—including engineering, product management, and customers—to align requirements and integration.
Mentoring engineers and sharing best practices.
Evaluating new technologies or architectural improvements .
Supporting IP integration and validation efforts.
Advance Synopsys’ leadership in memory PHY innovation.
Drive efficient power modeling practices that enhance product performance and competitiveness.
Take ownership of outcomes, ensuring projects meet and exceed expectations.
Shape future technology and product direction.
Support robust, scalable architectures.
Foster a collaborative and inclusive team culture across large, multidisciplinary groups.
Deliver solutions trusted by leading semiconductor companies.
15+ years in memory PHY architecture and power modeling.
Expertise with industry-standard design and simulation tools, including Power Artist and PTPX.
Proven experience driving efficient power models and taking responsibility for outcomes.
BSEE/MSEE required .
Strong analytical and communication skills .
Strong digital and/or analog design skills
Ability to work effectively with large cross-functional teams.
Strategic, collaborative, and detail-oriented .
Inclusive leader and effective communicator.

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: avature
Effort: medium

Benefits

Benefits detected in the listing.

Wellness