Job description

RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: No CLEARANCE TYPE: Top Secret TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. Northrop Grumman Mission Systems is a trusted provider of mission‑enabling solutions for global security. Our Engineering and Sciences (E&S) organization pushes the boundaries of innovation, redefines engineering capabilities, and drives advances in various sciences. Our team is chartered with providing the skills and innovative technologies to develop, design, produce, and sustain optimized product lines across the sector while providing a decisive advantage to the warfighter. Come be a part of our mission! We are looking for you to join our team as a Principal / Sr. Principal PCB Layout Design Engineer based out of Woodland Hills, CA . As a Principal / Sr. Principal PCB Layout Design Engineer at Northrop Grumman, you will have a challenging and rewarding opportunity to support the design and delivery of high‑reliability circuit card assemblies for aerospace, defense, and space flight applications. You will collaborate across electrical, mechanical, manufacturing, and signal integrity disciplines to transform complex electrical architectures and schematics into robust, production‑ready printed circuit board solutions. The successful candidate will be collaborative, open, and team‑oriented, with a focus on shared responsibility, continuous learning, and a culture of innovation and technical excellence. For this role, responsibilities include but are not limited to: • Execute the placement and routing of complex, high‑density, multi‑layer printed circuit boards (PCBs), including high‑speed digital, RF, mixed‑signal, and power circuits • Interpret electrical schematics, constraints, and mechanical boundaries to develop optimized PCB layouts that meet performance, reliability, and manufacturability requirements • Generate and maintain complete PCB and circuit card assembly (CCA) fabrication and assembly documentation packages, including artwork, drawings, fabrication notes, and data outputs for procurement and assembly partners • Apply current IPC and high‑reliability industry standards, as well as applicable military and aerospace criteria, in the design and verification of printed wiring boards and circuit card assemblies • Collaborate closely with electrical, mechanical, manufacturing, and signal integrity engineers to address layout‑related design challenges involving signal integrity, power integrity, thermal management, and packaging • Support and perform Design for Manufacturing (DFM), Design for Assembly (DFA), and Design for Test (DFT) reviews using automated and manual checks to improve yield, test coverage, and product robustness • Work with fabrication and assembly suppliers to understand manufacturing capabilities and constraints and incorporate them into PCB designs • Support PCB library management practices, ensuring correct use of symbols, footprints, and parameter data in accordance with internal workflows • (Principal) Independently own PCB layout tasks from concept through fabrication data release in support of program cost, schedule, and technical requirements • (Sr. Principal) Lead advanced PCB layout efforts using technologies such as High‑Density Interconnect (HDI), microvias, via‑in‑pad, backdrilling, and specialized substrate materials; provide technical guidance, peer reviews, and mentoring to other layout designers This position will require on‑site work at the Woodland Hills, CA facility . This requisition may be filled at either a Principal Level or a Sr. Principal Level. This requisition may be filled at a higher grade based on qualifications listed below. Basic Qualifications for a Principal PCB Layout Design Engineer (T03) • Bachelor’s degree in an engineering discipline with 5 years of engineering experience in an aerospace or closely related environment; or Master’s degree in an engineering discipline with 2 years of relevant experience • Ability to obtain and maintain a TS/SCI clearance • Willingness and ability to work on‑site full‑time at the Woodland Hills, CA location • Minimum 3 years of experience performing engineering/layout of printed circuit boards using Cadence Allegro or a closely related enterprise PCB layout tool • Experience with the layout of multi‑layer, high‑density PCBs and circuit card assemblies, including placement and routing of high‑speed digital, RF, and/or mixed‑signal circuits • Experience collaborating with diverse stakeholders across organizations and programs, including electrical design, mechanical design, manufacturing, test, and/or signal integrity • Working knowledge of PCB fabrication and assembly processes, including common manufacturability and yield considerations • Familiarity with IPC industry standards for PCB design and fabrication and current understanding of high‑reliability criteria • Experience generating artwork and PCB/CCA documentation for procurement and assembly houses • Excellent organizational and problem‑solving skills with a demonstrated ability to adapt effectively to changing requirements Basic Qualifications for a Sr. Principal PCB Layout Design Engineer (T04) • Bachelor’s degree in an engineering discipline with 8 years of engineering experience in an aerospace or closely related environment; or Master’s degree in an engineering discipline with 6 years of relevant experience; or PHD in an engineering discipline with 4 years of relevant exterience • Ability to obtain and maintain a TS/SCI clearance • Willingness and ability to work on‑site full‑time at the Woodland Hills, CA location • Minimum 3 years of experience performing engineering/layout of printed circuit boards using Cadence Allegro or a closely related enterprise PCB layout tool • Experience with the layout of multi‑layer, high‑density PCBs and circuit card assemblies, including placement and routing of high‑speed digital, RF, and/or mixed‑signal circuits • Experience collaborating with diverse stakeholders across organizations and programs, including electrical design, mechanical design, manufacturing, test, and/or signal integrity • Working knowledge of PCB fabrication and assembly processes, including common manufacturability and yield considerations • Familiarity with IPC industry standards for PCB design and fabrication and current understanding of high‑reliability criteria • Experience generating artwork and PCB/CCA documentation for procurement and assembly houses • Excellent organizational and problem‑solving skills with a demonstrated ability to adapt effectively to changing requirements Preferred Qualifications • Experience with signal integrity or power integrity analysis tools and workflows • Experience supporting environmental qualification and reliability test campaigns from a PCB layout perspective • Prior experience on defense or space flight programs with stringent reliability, documentation, and traceability requirements • Minimum 6+ years of experience performing engineering/layout of printed circuit boards using Cadence Allegro or a closely related enterprise PCB layout tool • Demonstrated expertise in the layout of advanced, high‑density, multi‑layer (typically 24+ layers) printed circuit boards combining RF, high‑speed digital, and high‑power circuit sections • Knowledge of PCB process workflows and library management, including creation and governance of symbols, footprints, and reusable layout elements • Experience implementing advanced manufacturing technologies, including High‑Density Interconnect (HDI), microvias, via‑in‑pad, backdrilling, and specialized substrate materials • Proven experience conducting comprehensive DFM, DFA, and DFT reviews using automated tools and collaborating with manufacturing and test partners to maximize manufacturing yields and test coverage • Experience providing technical guidance, layout reviews, and skill‑development mentorship to junior and mid‑level layout designers • Ability to translate complex mechanical boundaries and electrical constraints into optimized physical PCB layouts across multiple boards or modules • Deep domain knowledge of high‑reliability military and aerospace hardware criteria (e.g., MIL‑PRF‑31032, MIL‑STD‑883, IPC Class 3/3A), or comparable experience demonstrating equivalent rigor Primary Level Salary Range: $114,000.00 - $171,000.00 Secondary Level Salary Range: $142,200.00 - $213,400.00 The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions. Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business. The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates. Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit northropgrumman.com. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.

Requirements

Must-haves

RELOCATION ASSISTANCE: Relocation assistance may be available
CLEARANCE REQUIRED FOR START: No
CLEARANCE TYPE: Top Secret
TRAVEL: Yes, 10% of the Time Description
For this role, responsibilities include but are not limited to:
Execute the placement and routing of complex, high‑density, multi‑layer printed circuit boards (PCBs), including high‑speed digital, RF, mixed‑signal, and power circuits
Interpret electrical schematics, constraints, and mechanical boundaries to develop optimized PCB layouts that meet performance, reliability, and manufacturability requirements
Generate and maintain complete PCB and circuit card assembly (CCA) fabrication and assembly documentation packages, including artwork, drawings, fabrication notes, and data outputs for procurement and assembly partners
Apply current IPC and high‑reliability industry standards, as well as applicable military and aerospace criteria, in the design and verification of printed wiring boards and circuit card assemblies
Collaborate closely with electrical, mechanical, manufacturing, and signal integrity engineers to address layout‑related design challenges involving signal integrity, power integrity, thermal management, and packaging
Support and perform Design for Manufacturing (DFM), Design for Assembly (DFA), and Design for Test (DFT) reviews using automated and manual checks to improve yield, test coverage, and product robustness
Work with fabrication and assembly suppliers to understand manufacturing capabilities and constraints and incorporate them into PCB designs
Support PCB library management practices, ensuring correct use of symbols, footprints, and parameter data in accordance with internal workflows

Nice-to-haves

Experience with signal integrity or power integrity analysis tools and workflows
Experience supporting environmental qualification and reliability test campaigns from a PCB layout perspective
Prior experience on defense or space flight programs with stringent reliability, documentation, and traceability requirements
Demonstrated expertise in the layout of advanced, high‑density, multi‑layer (typically 24+ layers) printed circuit boards combining RF, high‑speed digital, and high‑power circuit sections
Knowledge of PCB process workflows and library management, including creation and governance of symbols, footprints, and reusable layout elements
Experience implementing advanced manufacturing technologies, including High‑Density Interconnect (HDI), microvias, via‑in‑pad, backdrilling, and specialized substrate materials
Proven experience conducting comprehensive DFM, DFA, and DFT reviews using automated tools and collaborating with manufacturing and test partners to maximize manufacturing yields and test coverage
Experience providing technical guidance, layout reviews, and skill‑development mentorship to junior and mid‑level layout designers
Ability to translate complex mechanical boundaries and electrical constraints into optimized physical PCB layouts across multiple boards or modules
Deep domain knowledge of high‑reliability military and aerospace hardware criteria (e.g., MIL‑PRF‑31032, MIL‑STD‑883, IPC Class 3/3A), or comparable experience demonstrating equivalent rigor
The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: eightfold
Effort: medium

Benefits

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Health Insurance

Pto

Paid Time Off