Job description

About SK hynix America: At SK hynix America, we are at the forefront of semiconductor innovation. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers. With major investments in the U.S. and a leading position in the global AI revolution, we build the critical infrastructure of the digital landscape and remain committed to sustainable operations. We invite innovative minds to be part of our journey. Here, you will be part of a collaborative team pioneering the next generation of memory technologies, expanding our market footprint, and defining the future of computing. Work Model: Onsite Job Title: HBM Logic Architect Office Location: San Jose, CA Job Type: Full-Time Work Model: Onsite Responsibilities: Define, design, and validate digital IP for ASIC/SoC products. Perform RTL design and implementation based on approved specifications. Collaborate with cross-functional teams to define IP functionality, behavior, and architecture. Review digital IP requirements and evaluate architecture options based on PPA targets. Determine or contribute to architecture decisions for digital IP implementation. Develop and verify RTL designs using industry-standard design methodologies. Provide design guidance and support for physical design implementation. Strengthen digital IP design capabilities for HBM and next-generation DRAM development by securing personnel for real-time support near customer sites. Drive system-level co-optimization beyond standalone DRAM design. Build deep technical partnerships with U.S.-based customers. Improve competitiveness through close engagement with customers in the U.S. Qualifications: Bachelor’s degree or higher in Electrical Engineering or a related discipline(Master’s preferred). 5+ years of relevant experience in semiconductor, ASIC/SoC, digital IP, memory, or PHY design. High-speed digital PHY or high-speed IP design and analysis DRAM memory controller design and analysis DRAM DFT/DFD architecture, design, or analysis PHY/TSV bit macro design, TSV PHY hard macro design, or 3D PHY design Experience in PPA (Power, Performance, Area) optimization, preferred. Benefits: Top Tier health insurance at no employee cost Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays 401k Matching Flexible Spending Account (FSA) for Health Care & Dependent Care Educational reimbursement up to $10,000 per year Donation Matching and volunteering opportunities Corporate discount programs Free Breakfast/Lunch/Dinner provided to employees Compensation: Our compensation reflects the cost of labor across several U.S. geographic markets, and we pay differently based on those defined markets. Pay within the provided range varies by work location and may also depend on job-related skills and experience. Your Recruiter can share more about the specific salary range for the job location during the hiring process. Pay Range $150,000 — $320,000 USD Equal Employment Opportunity: SK hynix America is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees and prohibit discrimination and harassment of any type without regard to race, sex, pregnancy, sexual orientation, religion, age, gender identity, national origin, color, protected veteran or disability status, genetic information, or any other status protected under federal, state, or local applicable laws. In compliance with federal law, SK hynix America also participates in the federal E-Verify program. Upon accepting an offer of employment, all newly hired individuals will be required to complete Form I-9, which includes verifying identity and legal authorization to work in the United States. Please review the official government posters detailing your rights and protections prior to applying: E-Verify Participation Poster (Bilingual English & Spanish) IER Right to Work Poster (English) IER Right to Work Poster (Spanish)

Requirements

Must-haves

Define, design, and validate digital IP for ASIC/SoC products.
Perform RTL design and implementation based on approved specifications.
Collaborate with cross-functional teams to define IP functionality, behavior, and architecture.
Review digital IP requirements and evaluate architecture options based on PPA targets.
Determine or contribute to architecture decisions for digital IP implementation.
Develop and verify RTL designs using industry-standard design methodologies.
Provide design guidance and support for physical design implementation.
Strengthen digital IP design capabilities for HBM and next-generation DRAM development by securing personnel for real-time support near customer sites.
Drive system-level co-optimization beyond standalone DRAM design.
Build deep technical partnerships with U.S.-based customers.
Improve competitiveness through close engagement with customers in the U.S.
5+ years of relevant experience in semiconductor, ASIC/SoC, digital IP, memory, or PHY design.
High-speed digital PHY or high-speed IP design and analysis
DRAM memory controller design and analysis
DRAM DFT/DFD architecture, design, or analysis
PHY/TSV bit macro design, TSV PHY hard macro design, or 3D PHY design

Nice-to-haves

Bachelor’s degree or higher in Electrical Engineering or a related discipline(Master’s preferred).
Experience in PPA (Power, Performance, Area) optimization, preferred.

Application prep

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Keywords to mirror

Platform: greenhouse
Effort: quick

Benefits

Benefits detected in the listing.

Health Insurance

401k

Paid Time Off

Parental Leave