Job description

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of timing signoff, and you know the difference between a clean sign-off and one that comes back to haunt you three weeks before tapeout. You understand that static timing analysis is not just about running PrimeTime—it is about understanding what the silicon will actually do when variation, IR drop, temperature, and aging all hit at once. You have debugged enough false paths and multi-cycle exceptions to know when a constraint deck is solid and when it is held together with hope. You are equally comfortable sitting with an R&D architect discussing distributed STA algorithms and walking a customer's design team through a HyperGrid deployment that just cut their runtime by 40%. When Intel, NVIDIA, Broadcom, Qualcomm, or a hyperscaler hits a blocker two weeks before their signoff milestone, you are the person they call because you will find the path through—whether that means a creative workaround, a targeted fix, or a hard conversation about what is actually achievable. You do not just react to problems, you see them coming. You connect dots between what customers are struggling with today and what the product roadmap needs to solve tomorrow. At Synopsys, you will shape the future of the industry's most widely deployed timing signoff solution, influencing designs that power everything from data centers to mobile devices. What You'll Be Doing • Drive production deployment of PrimeTime capabilities including HyperGrid distributed STA, native IR-aware timing analysis, thermal-aware signoff, aging analysis, and multi-die timing closure at strategic semiconductor customers and hyperscalers • Lead direct technical engagements with design teams at accounts like Intel, NVIDIA, Broadcom, Qualcomm, and cloud silicon teams, translating their advanced-node challenges into concrete product requirements, deployment strategies, and success metrics • Partner with R&D teams to evaluate and deploy emerging capabilities like AI-assisted Tcl generation and ML-based corner optimization, validating functionality in real customer environments, identifying performance bottlenecks, and driving resolution of complex product issues • Own beta programs and pre-production evaluations from kickoff through production readiness, defining test plans, tracking results across diverse design styles and process nodes, and ensuring customer success criteria are met • Resolve critical customer escalations through structured root-cause analysis, building effective workarounds when needed and driving long-term fixes back into the product with clear priority and business justification • Translate deployment experience, competitive intelligence, and customer feedback into clear roadmap recommendations for Product Management and engineering leadership, backed by data from real production use cases • Create technical content including deployment guides, best-practice methodologies, executive briefings, and training materials that accelerate adoption across the field organization and customer base The Impact You Will Have • Enable customers to achieve timing signoff on designs that would otherwise miss their tapeout windows, directly affecting product launch schedules for chips powering AI accelerators, automotive systems, mobile processors, and cloud infrastructure • Shape the PrimeTime roadmap by connecting real customer pain points with engineering priorities, ensuring development resources focus on capabilities that will drive the most adoption across the industry's most demanding design teams • Accelerate time-to-production for next-generation capabilities like ML-based corner optimization and AI-assisted workflows, turning early-stage features into deployed solutions that customers trust for production signoff • Build reusable deployment methodologies that scale across the customer base—from established semiconductor companies to hyperscalers building custom silicon—turning one successful engagement into a repeatable playbook • Strengthen Synopsys competitive position in timing signoff by ensuring customers see measurable value from advanced features before competitors can catch up, protecting and expanding PrimeTime's market leadership • Mentor Application and Product Engineers across the organization, raising the technical bar and building institutional knowledge around complex signoff challenges that will benefit the entire field team • Influence the architecture of future PrimeTime releases by representing real-world deployment constraints and customer workflows in early design discussions, ensuring new capabilities are built for how customers actually work What You'll Need • BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline • Deep hands-on experience with PrimeTime or comparable timing signoff tools across multiple production tapeouts, including multi-corner multi-mode analysis, variation modeling, and advanced-node signoff challenges • Strong understanding of static timing analysis fundamentals including setup/hold analysis, clock domain crossing, false paths, multi-cycle paths, and constraint methodology—you should be able to debug why a timing path is failing and know whether the issue is real or an artifact • Proficiency in Tcl and Python for automation, analysis, and debugging of complex timing scenarios, with code that other engineers can maintain • Track record of solving hard technical problems in EDA, ASIC/SoC design, or physical implementation environments where the answer was not obvious and the stakes were high • Experience with distributed computing, cloud infrastructure, or HyperGrid technologies is a strong plus • Background deploying new EDA technologies at semiconductor companies, including managing beta programs, customer training, or production readiness activities is highly valued • Experience working with leading semiconductor companies or hyperscalers on advanced-node designs (5nm and below) is a significant advantage Who You Are • You can walk into a room where a customer's timing closure is stuck and within an hour identify whether the issue is in their constraints, their methodology, the tool, or their design—and you know how to have that conversation without pointing fingers • When R&D proposes a new algorithm, you immediately think about how it will behave on a real customer design with 500 modes, 200 corners, and a constraint deck that has evolved over three years across multiple design teams • You write Tcl and Python that other engineers can actually read and modify six months later, because you know that one-off scripts become production infrastructure • You can explain a complex timing analysis tradeoff to a VP in two sentences without losing the technical nuance, and you can turn around and debug a multi-threaded race condition with an engineer the next hour • When you commit to a customer delivery date or an internal milestone, people know it will happen because you build in contingency and you escalate early when something is at risk • You push back when a product plan does not account for real deployment complexity, and you do it in a way that moves the conversation forward rather than shutting it down • You are energized by working with the best design teams in the industry—the engineers at Intel, NVIDIA, Broadcom, Qualcomm, and hyperscalers who are pushing the limits of what is possible in silicon The Team You'll Be Part Of You will join the PrimeTime Product Engineering team, reporting to the Product Engineering Manager. This team sits at the strategic center of PrimeTime development, working at the intersection of R&D, Product Management, and customer-facing Application Engineering. Your time will be split between customer-facing technical leadership (driving deployments, resolving escalations, leading beta programs), internal R&D partnership (evaluating new capabilities, validating performance, influencing architecture), and strategic roadmap work (translating customer needs into product priorities). This is not a pure customer-facing role and not a pure R&D role—it requires someone who can context-switch between both worlds effectively. The team is currently going through a reorganization that may expand your scope to include mentoring and leading other Product Engineers as the organization scales. If you have leadership aspirations beyond pure technical contribution, there will be opportunities to grow in that direction. You will be working on the industry's most widely deployed timing signoff solution, used by every major semiconductor company and hyperscaler. The decisions you make and the priorities you set will ripple across the entire semiconductor industry. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

Requirements

Must-haves

What You'll Be Doing
Resolve critical customer escalations through structured root-cause analysis, building effective workarounds when needed and driving long-term fixes back into the product with clear priority and business justification
Translate deployment experience, competitive intelligence, and customer feedback into clear roadmap recommendations for Product Management and engineering leadership, backed by data from real production use cases
Create technical content including deployment guides, best-practice methodologies, executive briefings, and training materials that accelerate adoption across the field organization and customer base
The Impact You Will Have
Accelerate time-to-production for next-generation capabilities like ML-based corner optimization and AI-assisted workflows, turning early-stage features into deployed solutions that customers trust for production signoff
Strengthen Synopsys competitive position in timing signoff by ensuring customers see measurable value from advanced features before competitors can catch up, protecting and expanding PrimeTime's market leadership
Mentor Application and Product Engineers across the organization, raising the technical bar and building institutional knowledge around complex signoff challenges that will benefit the entire field team
What You'll Need
BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline
Deep hands-on experience with PrimeTime or comparable timing signoff tools across multiple production tapeouts, including multi-corner multi-mode analysis, variation modeling, and advanced-node signoff challenges
Proficiency in Tcl and Python for automation, analysis, and debugging of complex timing scenarios, with code that other engineers can maintain
Track record of solving hard technical problems in EDA, ASIC/SoC design, or physical implementation environments where the answer was not obvious and the stakes were high
Experience with distributed computing, cloud infrastructure, or HyperGrid technologies is a strong plus
Background deploying new EDA technologies at semiconductor companies, including managing beta programs, customer training, or production readiness activities is highly valued
Experience working with leading semiconductor companies or hyperscalers on advanced-node designs (5nm and below) is a significant advantage
You write Tcl and Python that other engineers can actually read and modify six months later, because you know that one-off scripts become production infrastructure
You can explain a complex timing analysis tradeoff to a VP in two sentences without losing the technical nuance, and you can turn around and debug a multi-threaded race condition with an engineer the next hour
When you commit to a customer delivery date or an internal milestone, people know it will happen because you build in contingency and you escalate early when something is at risk
You push back when a product plan does not account for real deployment complexity, and you do it in a way that moves the conversation forward rather than shutting it down
You are energized by working with the best design teams in the industry—the engineers at Intel, NVIDIA, Broadcom, Qualcomm, and hyperscalers who are pushing the limits of what is possible in silicon
The Team You'll Be Part Of
Rewards and Benefits

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