Job description

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact In this position you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Storage, Security, and Networking. You’ll be part of the 3rd party IP management team. What You Can Expect In this role, you will work in parallel with a team of 3rd party IP engineers responsible for bringing in all subcontracted IP under the Marvell IP umbrella. This is a dynamic and challenging role, and, in this position, you will engage all parts of Marvell. Looking for a talented 3rd party IP integration engineer to assist Marvell in offering DDR/LPDDR/GDDR/HBM/eMMC memory interface cores to our clients. Become part of a team creating leading-edge designs for the latest applications in artificial intelligence, hyper-scaler, communications, and storage. As a 3rd party core integrator, you will be involved in all stages of SoC development including defining core requirements, validating IP developer competence, overseeing core development, technology compliance, core integration, test compliance and silicon validation. in this role you will: Assist sales in winning bids by working with leading edge IP providers to meet customer requirements. Manage 3rd party developers in completing core designs and providing required design rules. Advise the Marvell design center on core integration into custom silicon designs and hold joint reviews with the design center and 3rd party IP provider. Responsibilities will also include developing statements of work, leading provider progress reviews, using 3rd party developer problem reporting tools to drive to problem resolution. Assist with 8D follow-through for significant supplier issues. What We re Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience. Proficient in understanding of DDR type interfaces (DDR, LPDDR, GDDR, HBM, eMMC), including the challenges associated with SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging Proficient in project management tasks required to manage 3rd party developers Broad-based exposure to ASIC design flows required for releasing a chip to fabrication including logic synthesis, physical design, timing, DRC/LVS, Formal verification and electrical checking Good understanding of Design-For-Test concepts including DFT logic insertion, test generation, scan and embedded core testing Good communication and customer management skills Post-silicon validation at customer sites will require a limited degree of travel. Expected Base Pay Range (USD) 0 - 0, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps marvell.com . Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-TM1

Requirements

Must-haves

Assist sales in winning bids by working with leading edge IP providers to meet customer requirements.
Manage 3rd party developers in completing core designs and providing required design rules.
Assist with 8D follow-through for significant supplier issues.
What We re Looking For
Proficient in understanding of DDR type interfaces (DDR, LPDDR, GDDR, HBM, eMMC), including the challenges associated with SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging
Proficient in project management tasks required to manage 3rd party developers
Broad-based exposure to ASIC design flows required for releasing a chip to fabrication including logic synthesis, physical design, timing, DRC/LVS, Formal verification and electrical checking
Good understanding of Design-For-Test concepts including DFT logic insertion, test generation, scan and embedded core testing
Good communication and customer management skills
Post-silicon validation at customer sites will require a limited degree of travel.
0 - 0, $ per annum
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps marvell.com .
Interview Integrity

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

Platform: workday
Effort: long