Systems Software Engineer at Majestic Labs

Job description

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position We’re looking for a systems software engineer to work on the lowest layers of that stack: the runtime, firmware, and device software that sit between high-level AI workloads and custom accelerator hardware. You’ll help build the software responsible for device bring-up, kernel dispatch, memory mapping, queueing, synchronization, performance monitoring, and debug infrastructure. This is not a conventional embedded firmware role. The work spans firmware, operating-system interfaces, simulator bring-up, accelerator runtime design, hardware/software contracts, and performance-critical execution paths. Responsibilities • Own critical boot and runtime contracts: firmware image layout, configuration, core release, liveness detection, shared queues, command/completion formats, memory mappings, and versioned ABIs. • Build and optimize low-latency communication paths between host runtime software and accelerator cores, including submission/completion queues, doorbells, interrupts, polling paths, and synchronization mechanisms. • Work with custom processor cores, multi-core coordination, traps/exceptions, page tables, protection mechanisms, MMIO, DMA, and accelerator memory hierarchies. • Develop observability and debug infrastructure for a complex distributed accelerator system, including boot metrics, hardware counters, trace capture, performance monitoring, debug paths, and failure diagnosis for hung or slow jobs. • Help shape the production device software architecture: the boundary between kernel-mode components, userspace runtime libraries, simulator backends, and hardware-native backends. • Collaborate closely with hardware architects, compiler/runtime engineers, kernel developers, and performance engineers to define the software/hardware contracts for future chips. • Debug issues that cross abstraction layers: AI graph execution, runtime scheduling, device queues, firmware, memory translation, interrupts, simulator behavior, and hardware state. Requirements • 5-10 years of experience building low-level systems software, firmware, runtimes, operating systems, device drivers, or accelerator software. • Strong C programming skills and comfort reading or writing assembly where needed. • Deep understanding of computer architecture fundamentals: CPU privilege modes, virtual memory, interrupts, atomics, caches, memory ordering, MMIO, DMA, and performance counters. • Experience with one or more of: processor firmware, ARM or RISC-V systems software, Linux kernel drivers, bare-metal firmware, bootloaders, hypervisors, RTOS internals, or accelerator runtimes. • Ability to design and maintain stable binary interfaces and versioned contracts between independently evolving software components. • Strong debugging instincts across hardware/software boundaries, including cases where the only available evidence is a memory dump, trace buffer, hardware counter, queue state, or simulator log. • Comfortable working in a fast-moving environment where simulators, firmware, drivers, runtime libraries, and hardware specs are evolving together. • Excellent communication skills and the ability to collaborate across hardware, compiler, runtime, and product teams. Preferred Qualifications • Experience with custom accelerators, GPUs, NPUs, SmartNICs, DPUs, or other complex SoCs. • Low-level firmware experience, especially privilege modes, control/status registers, traps, memory protection, virtual memory, multi-core boot, or hardware debug support. • Linux driver or userspace driver/runtime experience, including ioctl/mmap APIs, DMA, IRQ handling, polling vs interrupt tradeoffs, and zero-copy paths. • Experience with hardware trace and performance infrastructure such as ARM CoreSight, ETM/ETF/ETR, ATB funnels, hardware PMUs, trace encoders, or similar SoC observability systems. • Experience designing queue protocols, command buffers, completion queues, doorbells, synchronization objects, or low-latency producer/consumer systems. • Experience with simulator and silicon bring-up: QEMU, virtual platforms, SystemC, RTL simulation, FPGA/prototyping, or first-silicon debug. • Experience with modern build systems such Bazel, cross-compilation, freestanding toolchains, linker scripts, and hermetic build systems in general. We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Requirements

Must-haves

Own critical boot and runtime contracts: firmware image layout, configuration, core release, liveness detection, shared queues, command/completion formats, memory mappings, and versioned ABIs.
Build and optimize low-latency communication paths between host runtime software and accelerator cores, including submission/completion queues, doorbells, interrupts, polling paths, and synchronization mechanisms.
Work with custom processor cores, multi-core coordination, traps/exceptions, page tables, protection mechanisms, MMIO, DMA, and accelerator memory hierarchies.
Help shape the production device software architecture: the boundary between kernel-mode components, userspace runtime libraries, simulator backends, and hardware-native backends.
Collaborate closely with hardware architects, compiler/runtime engineers, kernel developers, and performance engineers to define the software/hardware contracts for future chips.
Debug issues that cross abstraction layers: AI graph execution, runtime scheduling, device queues, firmware, memory translation, interrupts, simulator behavior, and hardware state.
5-10 years of experience building low-level systems software, firmware, runtimes, operating systems, device drivers, or accelerator software.
Strong C programming skills and comfort reading or writing assembly where needed.
Deep understanding of computer architecture fundamentals: CPU privilege modes, virtual memory, interrupts, atomics, caches, memory ordering, MMIO, DMA, and performance counters.
Experience with one or more of: processor firmware, ARM or RISC-V systems software, Linux kernel drivers, bare-metal firmware, bootloaders, hypervisors, RTOS internals, or accelerator runtimes.
Ability to design and maintain stable binary interfaces and versioned contracts between independently evolving software components.
Strong debugging instincts across hardware/software boundaries, including cases where the only available evidence is a memory dump, trace buffer, hardware counter, queue state, or simulator log.
Comfortable working in a fast-moving environment where simulators, firmware, drivers, runtime libraries, and hardware specs are evolving together.
Excellent communication skills and the ability to collaborate across hardware, compiler, runtime, and product teams.

Nice-to-haves

Experience with custom accelerators, GPUs, NPUs, SmartNICs, DPUs, or other complex SoCs.
Low-level firmware experience, especially privilege modes, control/status registers, traps, memory protection, virtual memory, multi-core boot, or hardware debug support.
Linux driver or userspace driver/runtime experience, including ioctl/mmap APIs, DMA, IRQ handling, polling vs interrupt tradeoffs, and zero-copy paths.
Experience with hardware trace and performance infrastructure such as ARM CoreSight, ETM/ETF/ETR, ATB funnels, hardware PMUs, trace encoders, or similar SoC observability systems.
Experience designing queue protocols, command buffers, completion queues, doorbells, synchronization objects, or low-latency producer/consumer systems.
Experience with simulator and silicon bring-up: QEMU, virtual platforms, SystemC, RTL simulation, FPGA/prototyping, or first-silicon debug.
Experience with modern build systems such Bazel, cross-compilation, freestanding toolchains, linker scripts, and hermetic build systems in general.

Application prep

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Keywords to mirror

Platform: comeet
Effort: medium