Principal ASIC Design

What the role needs

• Micro-Architecture: Collaborate with the architecture team to define and refine the micro-architecture of next-generation FortiASICs.
• Verification & Coverage: Partner with Design Verification (DV) teams to review test plans, perform coverage analysis, and execute full-chip simulations.
• RTL & Design Implementation: Implement designs using SystemVerilog/Verilog HDL, conduct Lint/CDC reviews, perform logic synthesis, execute timing analysis, and manage IP integration.
• Physical Design & PPA: Work with physical design teams to verify constraints, optimize placement and routing, close timing, and achieve optimal Power, Performance, and Area (PPA).
• FPGA Prototyping: Emulate and prototype designs using FPGAs to execute complete debug and validation cycles.
• Bring-Up & Support: Participate in system/board-level bring-up, post-silicon debugging, and ongoing technical support.
• Execution & Collaboration: Act as a self-starter who manages time effectively while collaborating with a diverse, cross-functional engineering team.
• 8+ years of experience in high-performance networking or processor design.
• Proven track record of taking complex ASIC/FPGA designs from initial concept to mass production.
• Hands-on expertise in Verilog / SystemVerilog HDL coding, synthesis, and design verification.
• In-depth experience across the entire high-performance ASIC development lifecycle—from specification drafting through system bring-up.
• Strong understanding of SystemVerilog and UVM verification methodologies.

From the employer

Fortinet is looking for a passionate ASIC Designer to join our R&D team! As a key member of Fortinet’s ASIC design group, you will help architect and design our next-generation FortiASIC technology to accelerate the world’s most powerful network security systems. This role involves working on cutting-edge, high-performance ASIC design from initial specification through RTL implementation. You will play a leading role in developing next-generation AI powered network processing ASIC architecture, performing IP integration, and delivering chip-level RTL design and verification. The ideal candidate is self-motivated, thrives in fast-paced environments with challenging schedules, and possesses a strong technical foundation across all phases of the ASIC design lifecycle—including RTL design, chip-level verification, coverage analysis, and Static Timing Analysis (STA). Deep knowledge of computer networking, machine learning, LLM acceleration, and ASIC design methodologies is essential. Job Responsibilities • Micro-Architecture: Collaborate with the architecture team to define and refine the micro-architecture of next-generation FortiASICs. • Verification & Coverage: Partner with Design Verification (DV) teams to review test plans, perform coverage analysis, and execute full-chip simulations. • RTL & Design Implementation: Implement designs using SystemVerilog/Verilog HDL, conduct Lint/CDC reviews, perform logic synthesis, execute timing analysis, and manage IP integration. • Physical Design & PPA: Work with physical design teams to verify constraints, optimize placement and routing, close timing, and achieve optimal Power, Performance, and Area (PPA). • FPGA Prototyping: Emulate and prototype designs using FPGAs to execute complete debug and validation cycles. • Bring-Up & Support: Participate in system/board-level bring-up, post-silicon debugging, and ongoing technical support. • Execution & Collaboration: Act as a self-starter who manages time effectively while collaborating with a diverse, cross-functional engineering team. Qualifications & Experience • 8+ years of experience in high-performance networking or processor design. • Proven track record of taking complex ASIC/FPGA designs from initial concept to mass production. • Hands-on expertise in Verilog / SystemVerilog HDL coding, synthesis, and design verification. • In-depth experience across the entire high-performance ASIC development lifecycle—from specification drafting through system bring-up. • Strong understanding of SystemVerilog and UVM verification methodologies. • Strong background in AI/LLM accelerator or NPU (Neural Processing Unit) design. • Strong problem-solving skills, attention to detail, and a collaborative mindset with strong written and verbal communication skills. Preferred Qualifications: • Experience with Altera (Intel) / AMD Xilinx FPGA architectures, EDA tools, and IP portfolios. • Deep understanding of Ethernet protocols and the TCP/IP networking stack . • Experience in microprocessor architecture, programmable logic design, or custom domain-specific accelerators. Educational Requirements • B.S. or M.S. in Electrical Engineering (EE), Computer Engineering (CE), Computer Science (CS), or a related technical field. Must be authorized to work in the U.S. without sponsorship. The US base salary range for this full-time position is $192,000-$235,000. Fortinet offers employees a variety of benefits, including medical, dental, vision, life and disability insurance, 401(k), 11 paid holidays, vacation time, and sick time, as well as a comprehensive leave program. Wage ranges are based on various factors, including the labour market, job type, and job level. Exact salary offers will be determined by factors such as the candidate's subject knowledge, skill level, qualifications, experience, and geographic location. All roles are eligible to participate in the Fortinet equity program. Bonus eligibility is reviewed at the time of hire and annually at the Company’s discretion. Why Join Us: We encourage candidates from all backgrounds and identities to apply. We offer a supportive work environment and a competitive Total Rewards package to support you with your overall health and financial well-being. Embark on a challenging, enjoyable, and rewarding career journey with Fortinet. Join us in bringing solutions that make a meaningful and lasting impact to our 890,000+ customers around the globe.