ASIC Engineering Technical Leader

What the role needs

• Minimum Qualifications Bachelors 8 years of related experience, or Masters 6 years of related experience, or PhD 3 years of related experience
• Prior experience in ASIC/SoC physical design and implementation in advanced tech nodes
• Prior hands-on experience with the full physical design flow at block and/or chip level
• Prior hands-on expertise in EDA tool flows, back-end sign-off criteria, and workflow automation utilizing Python, TCL, and Shell scripts to maximize turnaround time and execution efficiency.
• Expertise in STA methodology, SDC timing constraint creation, analysis, and timing ECO generation for final sign-off timing closure.
• Solid physical design fundamentals with proven ability to identify, debug, and fix complex Electromigration (EM), IR drop, RC parasitic extraction, and crosstalk/glitch violations.
• Prior hands-on experience with functional equivalence checking and functional ECOs
• Prior experience in power grid design and optimization
• Good understanding of the Standard-Cell IP, memory compiler IP Selection Criteria
• Prior experience in integrating mixed-signal designs
• We are Cisco, and our power starts with you.
• Message to applicants applying to work in the U.S. and/or Canada:

From the employer

The application window is expected to close on: 11/30/2026 Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We re a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact Don t just watch the AI revolution happen—build the physical backbone powering it. As a Physical Design Engineer at Silicon One Optics, you will floorplan, tape out, and physically realize our next-gen 800G, 1.6T, and multi-terabit optical transceivers and driver ICs. You ll directly shape the silicon photonics that power hyper-scale AI/ML data centers worldwide. If you want your silicon in the most demanding networks on the planet, this is where you need to be. Full-Flow Ownership & First-Pass Tapeout: Lead end-to-end RTL-to-GDSII physical design implementation across advanced nodes, driving hierarchical floorplanning, complex mixed-signal macro placement, and signoff (STA, IR/EM, PV) to ensure first-pass silicon success. Methodology & Flow Innovation: Architect and scale digital implementation flows, leveraging custom TCL/Python automation and close EDA vendor partnerships to elevate QoR, optimize turnaround time, and improve team-wide productivity. Cross-Functional Design Convergence: Lead physical execution across PnR, CTS, MMMC timing closure, and ECO iterations, collaborating closely with RTL, Analog, DFT, Packaging, and CAD teams to resolve complex cross-domain bottlenecks. Minimum Qualifications Bachelors 8 years of related experience, or Masters 6 years of related experience, or PhD 3 years of related experience Prior experience in ASIC/SoC physical design and implementation in advanced tech nodes Prior hands-on experience with the full physical design flow at block and/or chip level Prior hands-on expertise in EDA tool flows, back-end sign-off criteria, and workflow automation utilizing Python, TCL, and Shell scripts to maximize turnaround time and execution efficiency. Preferred Qualifications Prior experience in closing designs with high-speed, high-density, macro-dominant, and I/O cell–intensive blocks Expertise in STA methodology, SDC timing constraint creation, analysis, and timing ECO generation for final sign-off timing closure. Solid physical design fundamentals with proven ability to identify, debug, and fix complex Electromigration (EM), IR drop, RC parasitic extraction, and crosstalk/glitch violations. Prior hands-on experience with functional equivalence checking and functional ECOs Prior experience in power grid design and optimization Good understanding of the Standard-Cell IP, memory compiler IP Selection Criteria Prior experience in integrating mixed-signal designs Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate s hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $186,900.00 - $307,800.00 Non-Metro New York state & Washington state: $166,300.00 - $274,100.00 * For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.