Job description

At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale. Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions. We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles. Cornelis Networks is looking for a Senior ASIC Design Engineering Manager to lead and grow our RTL design engineering team. Reporting to the VP of ASIC Engineering, with direct exposure to executive leadership, this leader will manage a team of talented design engineers and drive full-lifecycle development of Cornelis’ next-generation, high-performance networking ASICs. The role is accountable for building and driving RTL implementation schedules across all SoC subsystems and full-chip milestones. Success requires deep hands-on expertise in advanced RTL design implementation, methodologies, and SoC flows, from microarchitecture definition through RTL delivery, tape-out readiness, and cross-functional execution with Architecture, Design Verification, Emulation, and Physical Design. This leader will also own headcount planning, hiring, and organizational strategy to build a nimble, efficient, world-class design team. Exposure to AI-based design flows and methodology is preferred. This role is intended for a senior engineering leader who can combine hands-on ASIC RTL design expertise with disciplined program execution, cross-functional coordination, and team building at scale. Key Responsibilities Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting progress against committed plans. Utilize data-driven insights to predict schedule risks and proactively reallocate human resources to keep the project on track. Align RTL delivery schedules with DV and emulation enablement and manage feedback loops and dependencies efficiently. Facilitate physical design handoffs by ensuring design teams provide high-quality RTL and constraints that minimize timing-closure iterations. Track physical design feedback and delivery schedules to support physical design signoff and tape-out milestones. Lead long-term headcount planning and organizational design for the ASIC department. Identify skill gaps and execute global talent acquisition strategies that support the product roadmap. Minimum Qualifications 15+ years in the semiconductor industry, preferably in high performance designs on advanced technology nodes, with at least 5 years in people management B.S. or M.S. in Computer Engineering, Electrical Engineering, or related technical field, or equivalent practical experience Deep understanding of the interaction between Design, Verification, Emulation, and Physical Design teams. You must know "how the work gets done" to manage the people doing it. Proven ability to lead large engineering organizations through multiple full-cycle ASIC product launches in a remote environment. Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints. Strong technical expertise in microarchitecture development, RTL coding (Verilog/System Verilog), synthesis, STA/timing closure, physical design, and verification methodologies. Exposure to one or more industry standards/protocol stacks such as PCIe, Ethernet, UCIe, UALink. Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory). Preferred Qualifications Exposure to AI based design implementation and verification flows, scripting for automation, milestone tracking and flow integration Experience building globally distributed ASIC design teams and scaling engineering practices in a remote environment. Location: This is a remote position for employees residing within the United States. We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry. At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives. In addition to your base pay, you’ll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave. Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Requirements

Must-haves

This role is intended for a senior engineering leader who can combine hands-on ASIC RTL design expertise with disciplined program execution, cross-functional coordination, and team building at scale.
Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting progress against committed plans.
Utilize data-driven insights to predict schedule risks and proactively reallocate human resources to keep the project on track.
Align RTL delivery schedules with DV and emulation enablement and manage feedback loops and dependencies efficiently.
Lead long-term headcount planning and organizational design for the ASIC department. Identify skill gaps and execute global talent acquisition strategies that support the product roadmap.
Minimum Qualifications
15+ years in the semiconductor industry, preferably in high performance designs on advanced technology nodes, with at least 5 years in people management
B.S. or M.S. in Computer Engineering, Electrical Engineering, or related technical field, or equivalent practical experience
Deep understanding of the interaction between Design, Verification, Emulation, and Physical Design teams. You must know "how the work gets done" to manage the people doing it.
Strong technical expertise in microarchitecture development, RTL coding (Verilog/System Verilog), synthesis, STA/timing closure, physical design, and verification methodologies.
Exposure to one or more industry standards/protocol stacks such as PCIe, Ethernet, UCIe, UALink.
Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).

Nice-to-haves

Exposure to AI based design implementation and verification flows, scripting for automation, milestone tracking and flow integration
Experience building globally distributed ASIC design teams and scaling engineering practices in a remote environment.
Location: This is a remote position for employees residing within the United States.

Application prep

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Keywords to mirror

Platform: bamboohr
Effort: medium

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)

Paid Time Off