Job description

div]:pl-0 xl:[&>div]:border-l xl:[&>div]:pl-6 xl:first:[&>div]:border-none xl:[&>div]:border-grey-100 [&_div]:flex-1"> Category Algorithm & Architecture Location San Jose, CA Experience More than 6 Years Work Expe. Job Description About the team: MediaTek’s Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies that power the world's most advanced data centers. We are a dynamic group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions. Our team collaborates closely to push the boundaries of technology, ensuring optimal performance, power efficiency, and scalability for data center applications. Join our Data Center team and be a part of the technological revolution that is shaping the future of data centers. If you are passionate about innovation and have the expertise to drive strategic technology development, we would love to hear from you. Responsibilities: Lead research and development of package architecture for AI accelerators and data center products. Responsible for defining reference packaging architecture and methodology for high‑power, high‑bandwidth multi-chiplet systems, with emphasis on concept development, STCO modeling, and technology selection. Collaborate leader with a strong technical background in semiconductor packaging, metrology, and characterization, who will develop and maintain strong, strategic partnerships with internal engineering teams across packaging, reliability, test, technology integration, and product development, and build collaborative relationships with external partners to ensure alignment of technology and product roadmaps. Provide technical leadership and maintain a deep understanding of industry trends and advancements in semiconductor packaging and characterization. Lead architecture definition of advanced packaging solutions such as 2.5D/3D, CPO, IVR, and HSIO. Partner across silicon, SI/PI, thermal/mechanical, reliability, platform, and vendor teams. Main Requirements and Qualifications • M.S. or Ph.D. in Electrical Engineering or a related field. • • 10+ years of experience in packaging, metrology, characterization, and component validation • • Experience with wafer level processes, package assembly processes, and substrate technology. • • Experience with data collection and analysis, including statistical methods. • • Proficiency in using simulation tools and first principles modeling. • • Proficiency in scripting languages such as Python for design automation. • • Excellent communication skills. • • • Salary range: $190,000- $270,000. • • Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more. • • • MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. • #LI-WC2

Requirements

Must-haves

div]:pl-0 xl:[&>div]:border-l xl:[&>div]:pl-6 xl:first:[&>div]:border-none xl:[&>div]:border-grey-100 [&_div]:flex-1"> Category Algorithm & Architecture
Location San Jose, CA
Experience More than 6 Years Work Expe.
Lead research and development of package architecture for AI accelerators and data center products.
Responsible for defining reference packaging architecture and methodology for high‑power, high‑bandwidth multi-chiplet systems, with emphasis on concept development, STCO modeling, and technology selection.
Provide technical leadership and maintain a deep understanding of industry trends and advancements in semiconductor packaging and characterization.
Lead architecture definition of advanced packaging solutions such as 2.5D/3D, CPO, IVR, and HSIO. Partner across silicon, SI/PI, thermal/mechanical, reliability, platform, and vendor teams.
Main Requirements and Qualifications
M.S. or Ph.D. in Electrical Engineering or a related field.
10+ years of experience in packaging, metrology, characterization, and component validation
Experience with wafer level processes, package assembly processes, and substrate technology.
Experience with data collection and analysis, including statistical methods.
Proficiency in using simulation tools and first principles modeling.
Proficiency in scripting languages such as Python for design automation.
Excellent communication skills.

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aipython

Platform: careers-html
Effort: medium

Benefits

Benefits detected in the listing.

Health Insurance

401k

Parental Leave