Job description

div]:pl-0 xl:[&>div]:border-l xl:[&>div]:pl-6 xl:first:[&>div]:border-none xl:[&>div]:border-grey-100 [&_div]:flex-1"> Category Chip Design Location Austin, TX Experience More than 2 Years Work Expe. Education Master's Degree Job Description MediaTek is a global fabless semiconductor industry leader, providing solutions from the edge to the cloud and powering over 2 billion connected devices every year. Established in 1997, our leading-edge technologies keep the world connected and enhance everyday life. At the forefront of innovation, MediaTek drives advancements in transformative technologies such as AI, 5G/6G, Wi-Fi 8, and Embedded IoT. Our high-performance, power-efficient solutions form the foundation for a smarter, more connected world — enabling everything from smartphones, smart homes, and AI PCs to high-performance computing, automotive, embedded IoT systems, and AI data centers. As a trusted partner to the world's leading brands, we are committed to ensuring access to world-class technology for everyone. Our dedication to accelerating AI underscores our mission to enrich the future of humanity. We are looking for a Design-for-Test (DFT) Engineer to support high-performance (>4 GHz) CPU subsystems using the latest DFT methodologies and techniques. In this role, you will help define and implement DFT architectures to meet test coverage goals, generate and simulate test patterns, and support post-silicon validation activities. Key Responsibilities Contribute to DFT architecture definition and implementation for high-performance CPU subsystems. Generate test patterns and simulate them at gate level to validate correctness and coverage. Support post-silicon validation by generating, analyzing, and debugging failing patterns on silicon. Main Requirements and Qualifications • At least 6 months of hands-on experience with DFT methodologies, including scan insertion, scan compression, ATPG pattern generation, and at-speed testing. • Ability to debug DFT patterns using gate-level simulations (GLS). • Exposure to DFT architecture for complex designs (preferably CPU subsystems or SoCs) and understanding of how to meet test coverage goals. • Experience with industry-standard DFT tools such as Synopsys DFT Compiler and TetraMAX. • Excellent communication skills and ability to collaborate with teams across worldwide sites. • • Preferred Skills • • Demonstrated ability to develop and deploy new DFT methodologies. • Knowledge of JTAG and related test standards. • • Education & Graduation Requirement • • Pursuing a degree in Electrical Engineering, Computer Engineering, or a related field. • MUST be graduating in December 2026 or May 2027 (not later). • • Salary range: $107,600-$153,400 annually • • Employee may be eligible for performance bonus, short- and long-term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more. • • MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. • • #LI-BJ1

Requirements

Must-haves

div]:pl-0 xl:[&>div]:border-l xl:[&>div]:pl-6 xl:first:[&>div]:border-none xl:[&>div]:border-grey-100 [&_div]:flex-1"> Category Chip Design
Location Austin, TX
Experience More than 2 Years Work Expe.
Education Master's Degree
Contribute to DFT architecture definition and implementation for high-performance CPU subsystems.
Generate test patterns and simulate them at gate level to validate correctness and coverage.
Support post-silicon validation by generating, analyzing, and debugging failing patterns on silicon.
Main Requirements and Qualifications
At least 6 months of hands-on experience with DFT methodologies, including scan insertion, scan compression, ATPG pattern generation, and at-speed testing.
Ability to debug DFT patterns using gate-level simulations (GLS).
Exposure to DFT architecture for complex designs (preferably CPU subsystems or SoCs) and understanding of how to meet test coverage goals.
Experience with industry-standard DFT tools such as Synopsys DFT Compiler and TetraMAX.
Excellent communication skills and ability to collaborate with teams across worldwide sites.

Nice-to-haves

Demonstrated ability to develop and deploy new DFT methodologies.
Knowledge of JTAG and related test standards.
Education & Graduation Requirement
Pursuing a degree in Electrical Engineering, Computer Engineering, or a related field.
MUST be graduating in December 2026 or May 2027 (not later).

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Benefits

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Health Insurance

401k

Parental Leave