Job description

div]:pl-0 xl:[&>div]:border-l xl:[&>div]:pl-6 xl:first:[&>div]:border-none xl:[&>div]:border-grey-100 [&_div]:flex-1"> Category Chip Design Location San Diego, CA Experience More than 6 Years Work Expe. Job Description About MediaTek MediaTek is a global fabless semiconductor company powering nearly two billion connected devices annually with system-on-chip technologies. Its solutions span mobile, connectivity, home entertainment, IoT, automotive, and AI-enabled platforms, including market-leading Wi-Fi technologies. For more information, please visit www.mediatek.com. About the Team With MediaTek’s leadership in SoC design, the MediaTek GPU IP team is committed to developing industry-leading, feature-rich, and highly PPA-competitive graphics IP. Our GPU technology is deployed across flagship and mainstream mobile SoCs and is also a foundational technology for adjacent markets including laptops, IoT, AI, VR/AR, automotive, and custom ASIC applications. The team is expanding and hiring top GPU talent across multiple disciplines, including architecture, microarchitecture, RTL design, software drivers, compiler technology, performance modeling, power optimization, and silicon validation. Positions are available in our San Diego and San Jose offices. Position Overview We are seeking a Staff / Senior Staff GPU Engineer specializing in Shader System RTL Design and Microarchitecture to help define, design, and deliver next-generation GPU IP. The ideal candidate will have strong hands-on experience in GPU shader subsystem microarchitecture, RTL implementation, performance analysis, functional debug, and PPA optimization. You will drive the design and optimization of shader core pipelines, thread/warp/wave scheduling, instruction dispatch and issue, execution pipelines, register files, and operand collection. You will work closely with architecture, compiler, software driver, verification, performance modeling, physical design, and post-silicon teams to deliver high-performance, power-efficient GPU IP for mobile, automotive, laptop, IoT, AI, VR/AR, and ASIC markets. Role and Responsibilities • Define, develop, and own GPU shader subsystem microarchitecture specifications. • Lead RTL design for shader-related blocks, including shader pipelines, instruction issue, operand collection, register files, dependency tracking, and pipeline control. • Collaborate with architecture and compiler teams to translate ISA behavior, API requirements, shader workloads, and performance targets into efficient hardware designs. • Analyze GPU workloads and performance data to improve occupancy, throughput, latency hiding, register pressure, and power efficiency. • Support the full GPU IP lifecycle, including microarchitecture definition, RTL coding, lint/CDC/RDC cleanup, verification support, synthesis, timing closure, tape-out, bring-up, and post-silicon debug. • Partner with verification teams on test plans, coverage, assertions, debug strategies, and directed/random test scenarios. Main Requirements and Qualifications • Minimum Qualifications • • BS, MS, or PhD in Computer Science, Electrical Engineering, Computer Engineering, or related field, or equivalent practical experience. • • 8+ years of experience for Staff level, or 10+ years for Senior Staff level, in RTL design, microarchitecture, or architecture for GPU, graphics, processor, AI accelerator, DSP, or high-performance SoC subsystems. • • Strong hands-on experience with SystemVerilog, Verilog, VHDL, C/C++, and scripting languages such as Python, Perl, Tcl, or shell. • • Proven experience designing complex RTL blocks with strong understanding of timing, area, power, clocking, reset, CDC/RDC, low-power design, and synthesis constraints. • • Solid understanding of computer architecture, GPU architecture, processor pipelines, parallel execution models, memory hierarchy, interconnects, and performance/power trade-offs. • • Experience with RTL quality flows including lint, CDC, reset analysis, synthesis, formal checks, assertions, waveform debug, and regression debug. • • Ability to work effectively with architecture, verification, physical design, software, compiler, performance, and post-silicon teams. • • Preferred Qualifications • • Deep knowledge of GPU shader architectures, including SIMT/SIMD execution, instruction issue, register files, operand collection, execution pipelines, and latency hiding. • • Hands-on experience with one or more shader subsystem areas: pipeline design, instruction fetch/decode/dispatch/issue, register file banking, or dependency tracking. • • Experience with GPU graphics and compute workloads such as vertex, pixel/fragment, compute, mesh, geometry, tessellation, ray tracing, or AI/ML shaders. • • Knowledge of GPU ISA, shader compiler interaction, instruction scheduling, register allocation, occupancy, and compiler-hardware co-optimization. • • Experience with mobile GPU design, tile-based rendering, unified shader architectures, and low-power design. • • Salary range: $157,000- $256,000 • Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more. • MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. • #LI-NL1 • •

Requirements

Must-haves

div]:pl-0 xl:[&>div]:border-l xl:[&>div]:pl-6 xl:first:[&>div]:border-none xl:[&>div]:border-grey-100 [&_div]:flex-1"> Category Chip Design
Location San Diego, CA
Experience More than 6 Years Work Expe.
BS, MS, or PhD in Computer Science, Electrical Engineering, Computer Engineering, or related field, or equivalent practical experience.
8+ years of experience for Staff level, or 10+ years for Senior Staff level, in RTL design, microarchitecture, or architecture for GPU, graphics, processor, AI accelerator, DSP, or high-performance SoC subsystems.
Strong hands-on experience with SystemVerilog, Verilog, VHDL, C/C++, and scripting languages such as Python, Perl, Tcl, or shell.
Proven experience designing complex RTL blocks with strong understanding of timing, area, power, clocking, reset, CDC/RDC, low-power design, and synthesis constraints.
Solid understanding of computer architecture, GPU architecture, processor pipelines, parallel execution models, memory hierarchy, interconnects, and performance/power trade-offs.
Experience with RTL quality flows including lint, CDC, reset analysis, synthesis, formal checks, assertions, waveform debug, and regression debug.
Ability to work effectively with architecture, verification, physical design, software, compiler, performance, and post-silicon teams.

Nice-to-haves

Deep knowledge of GPU shader architectures, including SIMT/SIMD execution, instruction issue, register files, operand collection, execution pipelines, and latency hiding.
Hands-on experience with one or more shader subsystem areas: pipeline design, instruction fetch/decode/dispatch/issue, register file banking, or dependency tracking.
Experience with GPU graphics and compute workloads such as vertex, pixel/fragment, compute, mesh, geometry, tessellation, ray tracing, or AI/ML shaders.
Knowledge of GPU ISA, shader compiler interaction, instruction scheduling, register allocation, occupancy, and compiler-hardware co-optimization.
Experience with mobile GPU design, tile-based rendering, unified shader architectures, and low-power design.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aiapipythonml

Platform: careers-html
Effort: medium

Benefits

Benefits detected in the listing.

Health Insurance

401k

Pto

Parental Leave