Job description

div]:pl-0 xl:[&>div]:border-l xl:[&>div]:pl-6 xl:first:[&>div]:border-none xl:[&>div]:border-grey-100 [&_div]:flex-1"> Category Chip Design Location San Jose, CA Experience More than 4 Years Work Expe. Job Description We are building the memory subsystems for next-generation data center-class ASICs — large-scale, multi-reticle, chiplet-based 3D designs purpose-built for AI/ML training and inference, cloud compute, and networking infrastructure. We are looking for a 3DIC Memory DTCO Engineer to design and qualify high-bandwidth SRAM and embedded memory IP for these heterogeneous, multi-die 3DIC products. You will own memory macro design, physical implementation, and characterization for memories that must deliver high bandwidth and operate correctly across chiplets built on different process nodes, reticle-stitched or stacked and bonded together (hybrid bonding, TSV, or 2.5D/3D packaging), and connected through high-bandwidth die-to-die interfaces. This is a hands-on circuit and physical design role at the intersection of custom memory design, physical design/optimization, DTCO, cross-die timing signoff, and advanced packaging/3DIC co-design for data center-scale silicon. Key Responsibilities • Architect high-bandwidth embedded memory for multi-reticle, chiplet-based 3DIC systems — balancing die-to-die latency, bandwidth, power delivery, and thermal constraints across heterogeneous dies in data center accelerator and networking SoCs. • Own physical design and optimization for memory-heavy blocks: floorplanning, macro placement/tiling, power grid design, IR-drop/EM mitigation, and timing/congestion closure, including across reticle boundaries. • Plan power distribution across multiple power rails/voltage domains, define custom routing plans for memory and mixed-signal blocks, and drive TSV planning (placement, density, pitch, keep-out zones) with floorplanning, PDN, and package teams. • Drive DTCO with process/technology teams — tuning bitcell architecture, track height, contacted poly pitch, and metal stack choices against PPA and yield for memory-heavy, data center-scale dies. • Own cross-die timing signoff across the 3D stack-up: STA through TSVs/hybrid-bonding interconnect, setup/hold margining across die and reticle boundaries, closing timing under PVT, OCV/AOCV, and clock-skew variation. • Apply low-power techniques — voltage scaling, retention modes, power gating, near-threshold operation — for memories spanning chiplets with different power domains and data center power/thermal envelopes. • Run signal/power integrity analysis for high-bandwidth memory interfaces crossing die boundaries: IR drop, noise coupling, cross-die timing closure. • Develop and validate DFT/MBIST/repair schemes for embedded memories, supporting test and yield recovery in stacked-die, multi-reticle environments. • Drive silicon characterization, correlation, and debug of memory test chips and first-silicon bring-up; feed yield/reliability and bandwidth data (retention, SER, aging) back into design and DTCO decisions. • Collaborate cross-functionally with process/TCAD, packaging, physical design, timing signoff, DFT, and firmware teams across the product lifecycle. • Help evolve internal memory compiler/IP flows, PDKs, and 3DIC-aware design methodologies for multi-reticle, chiplet-based platforms. #LI-WC2 Main Requirements and Qualifications • Required Qualifications • • BS/MS/PhD in EE, CE, or related field; 5+ years (or equivalent depth at senior/staff level) of hands-on custom circuit/memory design experience. • • Experience designing high-bandwidth SRAM sense amps and periphery circuits at advanced process nodes (3nm and below preferred). • • Transistor-level analog/mixed-signal design skills using SPICE-class simulators (HSPICE, Spectre, FineSim) for characterization, Monte Carlo, and corner analysis. • • Physical design and optimization experience (floorplanning, P&R, clock tree, IR-drop/EM analysis) for memory-heavy blocks, resolving congestion, timing, and power trade-offs around large, high-bandwidth SRAM arrays. • • PDN planning across multiple power rails/voltage domains, custom routing planning for memory/mixed-signal blocks, and TSV planning (placement, pitch, density, keep-out rules) for 3D-stacked dies. • • DTCO experience — co-optimizing bitcell and standard-cell architecture, design rules, and process assumptions with technology teams against PPA and yield for memory-heavy dies. • • Multi-die/3D-IC timing signoff experience — cross-die STA, timing budgeting/margining across TSV/hybrid-bonding interfaces, closing setup/hold and clock-domain timing across dies (e.g., Synopsys PrimeTime 3DIC, Cadence Tempus 3D-IC, or equivalent). • • Working knowledge of 3DIC/advanced packaging — TSVs, hybrid bonding, micro-bumps, die-to-die interconnect — and their impact on memory design (parasitics, thermal gradients, mechanical stress). • • Familiarity with data center-class ASIC design — large/multi-reticle dies, high-power/high-thermal-density SoCs, and system-level constraints of AI/ML accelerators, cloud, or networking silicon. • • Familiarity with low-power methodologies (power gating, multi-Vt, voltage islands) and cross-domain power/clock considerations in multi-die systems. • • Layout-aware design experience with DRC/LVS closure and parasitic extraction for custom memory macros. • • Solid understanding of memory test, redundancy, and repair architectures (row/column redundancy, ECC, BIST). • Preferred / Bonus Qualifications • • Direct experience taping out or bringing up memory IP used in a chiplet-based or 3D-stacked data center ASIC (SoIC, CoWoS, Foveros-class packaging, or similar). • • Experience with multi-reticle die design — reticle stitching, cross-reticle floorplanning, or stepper/exposure-field constraints as they affect memory placement and routing. • • Exposure to heterogeneous integration where chiplets span different foundries/process nodes, including cross-node timing/power co-design. • What Success Looks Like • • Memory IP that meets high-bandwidth, power, and performance targets for data center-class ASICs while remaining robust across the thermal and mechanical variation introduced by multi-reticle 3D stacking. • • Physical implementation of memory-heavy blocks that closes timing, power, and congestion cleanly, with DTCO feedback that measurably improves PPA/yield on memory-dominated dies. • • Robust power distribution across all rails, routing plans and TSV placement that hold up under IR-drop/EM and mechanical stress analysis. • • Clean, signed-off timing across the full 3D stack-up and reticle boundaries, with cross-die paths closed under realistic margining and no late-stage surprises after die stacking. • • Silicon-validated memory macros with characterization data that closes the loop between simulation and measured results. • • Effective collaboration with packaging and cross-die interface teams, resulting in memory architectures that are repairable and yield-friendly after die stacking. • • To apply, please submit your resume along with a summary of relevant memory design and 3DIC/chiplet project experience. • • Salary range: $171,000- $286,000 • • Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more. • • MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. • • #LI-WC2

Requirements

Must-haves

div]:pl-0 xl:[&>div]:border-l xl:[&>div]:pl-6 xl:first:[&>div]:border-none xl:[&>div]:border-grey-100 [&_div]:flex-1"> Category Chip Design
Location San Jose, CA
Experience More than 4 Years Work Expe.
Own physical design and optimization for memory-heavy blocks: floorplanning, macro placement/tiling, power grid design, IR-drop/EM mitigation, and timing/congestion closure, including across reticle boundaries.
Drive DTCO with process/technology teams — tuning bitcell architecture, track height, contacted poly pitch, and metal stack choices against PPA and yield for memory-heavy, data center-scale dies.
Own cross-die timing signoff across the 3D stack-up: STA through TSVs/hybrid-bonding interconnect, setup/hold margining across die and reticle boundaries, closing timing under PVT, OCV/AOCV, and clock-skew variation.
Apply low-power techniques — voltage scaling, retention modes, power gating, near-threshold operation — for memories spanning chiplets with different power domains and data center power/thermal envelopes.
Run signal/power integrity analysis for high-bandwidth memory interfaces crossing die boundaries: IR drop, noise coupling, cross-die timing closure.
Develop and validate DFT/MBIST/repair schemes for embedded memories, supporting test and yield recovery in stacked-die, multi-reticle environments.
Drive silicon characterization, correlation, and debug of memory test chips and first-silicon bring-up; feed yield/reliability and bandwidth data (retention, SER, aging) back into design and DTCO decisions.
Collaborate cross-functionally with process/TCAD, packaging, physical design, timing signoff, DFT, and firmware teams across the product lifecycle.
Help evolve internal memory compiler/IP flows, PDKs, and 3DIC-aware design methodologies for multi-reticle, chiplet-based platforms.
Main Requirements and Qualifications
BS/MS/PhD in EE, CE, or related field; 5+ years (or equivalent depth at senior/staff level) of hands-on custom circuit/memory design experience.
Transistor-level analog/mixed-signal design skills using SPICE-class simulators (HSPICE, Spectre, FineSim) for characterization, Monte Carlo, and corner analysis.
Physical design and optimization experience (floorplanning, P&R, clock tree, IR-drop/EM analysis) for memory-heavy blocks, resolving congestion, timing, and power trade-offs around large, high-bandwidth SRAM arrays.
PDN planning across multiple power rails/voltage domains, custom routing planning for memory/mixed-signal blocks, and TSV planning (placement, pitch, density, keep-out rules) for 3D-stacked dies.
DTCO experience — co-optimizing bitcell and standard-cell architecture, design rules, and process assumptions with technology teams against PPA and yield for memory-heavy dies.
Working knowledge of 3DIC/advanced packaging — TSVs, hybrid bonding, micro-bumps, die-to-die interconnect — and their impact on memory design (parasitics, thermal gradients, mechanical stress).
Familiarity with data center-class ASIC design — large/multi-reticle dies, high-power/high-thermal-density SoCs, and system-level constraints of AI/ML accelerators, cloud, or networking silicon.
Familiarity with low-power methodologies (power gating, multi-Vt, voltage islands) and cross-domain power/clock considerations in multi-die systems.
Layout-aware design experience with DRC/LVS closure and parasitic extraction for custom memory macros.

Nice-to-haves

Experience designing high-bandwidth SRAM sense amps and periphery circuits at advanced process nodes (3nm and below preferred).
Preferred / Bonus Qualifications

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Health Insurance

401k

Parental Leave