Job description

Tier-1 Semiconductor Design House Location Woburn, MA Sector Semiconductors Type Permanent Starts Share Job description Analog/Mixed-Signal Layout Engineer (Woburn, MA) The client The client is a leading semiconductor design house specializing in advanced custom analog and mixed‑signal integrated circuits. With a global footprint and a strong focus on cutting‑edge FinFET technologies, they deliver high‑performance IP for a range of high‑speed applications across multiple markets. Backed by significant R&D investment, the organisation combines deep analog expertise with modern digital integration capabilities, offering engineers the opportunity to work on industry‑leading IP such as high‑speed ADCs, DACs, PLLs and RF front‑ends. The role Develop high‑quality custom layouts for complex analog and mixed‑signal blocks in advanced FinFET processes, collaborating closely with circuit designers to optimise performance. You will: • Create block‑level custom layouts for analog, mixed‑signal and RF circuits using Cadence Virtuoso • Perform LVS and DRC sign‑off with Calibre and run parasitic extraction (StarRC, QRC) • Apply advanced layout techniques to optimise matching, noise coupling, supply integrity and parasitic performance • Identify and mitigate layout‑dependent effects in 7nm and smaller FinFET technologies • Own assigned layout blocks from concept through to tape‑out and support integration across multiple sites • Contribute to methodology improvements and best‑practice documentation Your background • 6+ years of custom analog/mixed‑signal layout experience (minimum 2 years in 7nm FinFET block‑level layout) • Proficiency with Cadence Virtuoso and Calibre LVS/DRC tools • Experience with parasitic extraction tools such as StarRC or QRC • Strong understanding of layout‑dependent effects and mitigation strategies • Solid knowledge of analog and mixed‑signal circuit operation and performance considerations • Ability to work independently, take technical ownership and collaborate with cross‑functional teams Salary $000000 – $000000 Location Woburn, MA At PER International we believe the best engineering teams are also the most diverse. We welcome applications from candidates of every background, and assure every applicant that they will be assessed on the strength of their work and ambition — without regard to race, gender, religion, sexual orientation or disability. Apply for this role

Requirements

Must-haves

Tier-1 Semiconductor Design House
Location Woburn, MA
Sector Semiconductors
Type Permanent
Analog/Mixed-Signal Layout Engineer (Woburn, MA)
Develop high‑quality custom layouts for complex analog and mixed‑signal blocks in advanced FinFET processes, collaborating closely with circuit designers to optimise performance.
Create block‑level custom layouts for analog, mixed‑signal and RF circuits using Cadence Virtuoso
Perform LVS and DRC sign‑off with Calibre and run parasitic extraction (StarRC, QRC)
Apply advanced layout techniques to optimise matching, noise coupling, supply integrity and parasitic performance
Identify and mitigate layout‑dependent effects in 7nm and smaller FinFET technologies
Own assigned layout blocks from concept through to tape‑out and support integration across multiple sites
Contribute to methodology improvements and best‑practice documentation
6+ years of custom analog/mixed‑signal layout experience (minimum 2 years in 7nm FinFET block‑level layout)
Proficiency with Cadence Virtuoso and Calibre LVS/DRC tools
Experience with parasitic extraction tools such as StarRC or QRC
Strong understanding of layout‑dependent effects and mitigation strategies
Solid knowledge of analog and mixed‑signal circuit operation and performance considerations
Ability to work independently, take technical ownership and collaborate with cross‑functional teams
Apply for this role

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: careers-html
Effort: medium