Job description

div]:pl-0 xl:[&>div]:border-l xl:[&>div]:pl-6 xl:first:[&>div]:border-none xl:[&>div]:border-grey-100 [&_div]:flex-1"> Category Chip Design Location San Jose, CA Experience More than 8 Years Work Expe. Job Description MediaTek’s advanced memory design team in San Jose, CA is seeking a highly experienced memory design engineer to architect and define memory circuits. This role focuses on high-performance compute (HPC) ASIC solutions for Data Center AI and Networking, as well as designing energy efficient edge AI Accelerators. • Work in close partnership with leading Data Center AI ASIC customers in North America to co-develop embedded memory architectures and circuits on advanced technology nodes. • Collaborate with product engineering, technology development and architecture teams to define, design, and deliver high-performance, customized semiconductor memory solutions — including SRAM, TCAM, Compute-In-Memory (CIM), and Near Memory Compute (NMC) macros — tailored to diverse PPA requirements for Data Center AI, Networking, and Edge AI applications. • Lead Design Technology Co-Optimization (DTCO) and pathfinding initiatives for semi-custom and custom SRAM designs. • Lead the end-to-end design of dual-rail custom memories, ensuring all customer performance, power, and area (PPA) specifications are fully satisfied. • Drive innovation by designing and integrating specialized circuits and features to achieve industry-leading PPA in both custom and compiler-generated memories. • Provide mentorship and technical direction to other designers, while remaining hands-on in digital circuit design with a focus on memory architectures. • Evaluate and implement new design methodologies and tools to enhance productivity and quality. • Demonstrate strong organizational skills and the ability to work independently, effectively managing multiple tasks, and collaborating with global design and CAD teams. #LI-WC2 Main Requirements and Qualifications • • PhD or master's degree in electrical engineering or related field. • • 10+ years of hands-on experience designing embedded memories (SRAM, TCAM) for high-performance processors or ASICs in advanced technology nodes (A14/A16/2nm/3nm/5nm). • • Proven track record of delivering innovative solutions, including published papers and patents, with a strong understanding of the technology roadmap and market trends for embedded memories. • • Experience with DTCO and pathfinding for semi-custom and custom designs is desirable. • • Deep expertise in digital circuit design techniques, particularly in FinFET and Gate-All-Around technologies. • • Experience with the full design cycle of SRAM and memory compiler development. • • Skilled in developing comprehensive design verification and test plans. • • Familiarity with Logic Equivalence Checking (LEC) tools such as ESPCV. • • Capable of reviewing and coordinating layout activities & IR-EM signoff. • • Familiarity with transistor level STA tools such as NanoTime. • • Demonstrated experience in silicon debugging and bring-up. • • Experience with semi-custom design flows, including RTL synthesis, DV, APR, and STA, is desirable. • • Proficient in scripting languages such as Perl and Python. • • Strong analytical & problem-solving skills with excellent communication & leadership abilities. • • Eager to work collaboratively with cross-functional teams across global locations. • • • Salary range: $221,000 - $301,000 • • Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Paid time off (PTO), Parental leave, 401K and more. • • MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. •

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div]:pl-0 xl:[&>div]:border-l xl:[&>div]:pl-6 xl:first:[&>div]:border-none xl:[&>div]:border-grey-100 [&_div]:flex-1"> Category Chip Design
Location San Jose, CA
Experience More than 8 Years Work Expe.
Work in close partnership with leading Data Center AI ASIC customers in North America to co-develop embedded memory architectures and circuits on advanced technology nodes.
Lead Design Technology Co-Optimization (DTCO) and pathfinding initiatives for semi-custom and custom SRAM designs.
Lead the end-to-end design of dual-rail custom memories, ensuring all customer performance, power, and area (PPA) specifications are fully satisfied.
Drive innovation by designing and integrating specialized circuits and features to achieve industry-leading PPA in both custom and compiler-generated memories.
Provide mentorship and technical direction to other designers, while remaining hands-on in digital circuit design with a focus on memory architectures.
Evaluate and implement new design methodologies and tools to enhance productivity and quality.
Demonstrate strong organizational skills and the ability to work independently, effectively managing multiple tasks, and collaborating with global design and CAD teams.
Main Requirements and Qualifications
PhD or master's degree in electrical engineering or related field.
10+ years of hands-on experience designing embedded memories (SRAM, TCAM) for high-performance processors or ASICs in advanced technology nodes (A14/A16/2nm/3nm/5nm).
Proven track record of delivering innovative solutions, including published papers and patents, with a strong understanding of the technology roadmap and market trends for embedded memories.
Experience with DTCO and pathfinding for semi-custom and custom designs is desirable.
Deep expertise in digital circuit design techniques, particularly in FinFET and Gate-All-Around technologies.
Experience with the full design cycle of SRAM and memory compiler development.
Skilled in developing comprehensive design verification and test plans.
Familiarity with Logic Equivalence Checking (LEC) tools such as ESPCV.
Capable of reviewing and coordinating layout activities & IR-EM signoff.
Familiarity with transistor level STA tools such as NanoTime.
Demonstrated experience in silicon debugging and bring-up.
Experience with semi-custom design flows, including RTL synthesis, DV, APR, and STA, is desirable.
Proficient in scripting languages such as Perl and Python.

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