Job description

Leading Fabless Semiconductor Company Location Austin, Texas (Hybrid) Sector Semiconductors Type Permanent Starts Q3 2026 Share Job description IP DFT Engineer – Hybrid The client Our client is a leading global fabless semiconductor company developing advanced, high-performance and power-efficient technologies for a wide range of connected applications. The company operates at the forefront of areas including AI, wireless connectivity, mobile and computing technologies, with semiconductor solutions used across consumer electronics, smart devices, automotive, high-performance computing and data center applications. Working with major technology brands worldwide, the business offers engineers the opportunity to contribute to advanced semiconductor technologies used across global markets. The role This position will focus on developing and implementing Design for Test (DFT) strategies for mixed-signal IP blocks, ensuring high test coverage, testability, and manufacturability. You will work closely with analog, digital, verification, and integration teams throughout the IP development lifecycle. The current hybrid schedule is Monday through Thursday on-site, with Friday working remotely. You will: • Develop and implement DFT architectures and methodologies for mixed-signal IP blocks. • Perform scan insertion and test point insertion for digital portions of mixed-signal IP. • Develop test enablement strategies for analog and mixed-signal circuitry. • Collaborate with analog and digital design teams to incorporate DFT requirements during IP development. • Perform DFT verification, including ATPG, fault simulation, fault grading, and coverage analysis. • Support scan diagnosis and testability analysis. • Work with integration DFT teams to integrate IP-level DFT features into larger subsystems and SoCs. • Document DFT architecture, verification methodology, and test procedures. • Contribute to continuous improvement of mixed-signal DFT methodologies and best practices. Your background • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline. • 7+ years of experience in DFT implementation for digital, mixed-signal, or semiconductor IP. • Strong understanding of DFT concepts including scan/scan insertion, ATPG, JTAG, test point insertion, scan diagnosis, fault simulation/fault grading, and test coverage analysis. • Experience with industry-standard DFT and simulation tools such as Synopsys DFT Compiler, TetraMax, Siemens Tessent, VCS, or Verdi. • Familiarity with RTL design and simulation, including Verilog and/or VHDL. • Understanding of analog or mixed-signal design and test concepts. • Experience with ATPG, fault grading, and coverage analysis for digital logic. • Strong analytical, debugging, problem-solving, and communication skills. • Silicon debug and production test experience. • Scripting experience using Python, Perl, and/or Tcl. • Knowledge of hierarchical DFT and subsystem integration. • Understanding of low-power design and associated DFT challenges. • Experience working with mixed-signal semiconductor designs. • Experience collaborating across multi-site and cross-functional engineering teams. Location Austin, Texas Start date Q3 2026 At PER International we believe the best engineering teams are also the most diverse. We welcome applications from candidates of every background, and assure every applicant that they will be assessed on the strength of their work and ambition — without regard to race, gender, religion, sexual orientation or disability. Apply for this role

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Leading Fabless Semiconductor Company
Location Austin, Texas (Hybrid)
Sector Semiconductors
Type Permanent
Starts Q3 2026
IP DFT Engineer – Hybrid
Our client is a leading global fabless semiconductor company developing advanced, high-performance and power-efficient technologies for a wide range of connected applications.
Develop and implement DFT architectures and methodologies for mixed-signal IP blocks.
Perform scan insertion and test point insertion for digital portions of mixed-signal IP.
Develop test enablement strategies for analog and mixed-signal circuitry.
Collaborate with analog and digital design teams to incorporate DFT requirements during IP development.
Perform DFT verification, including ATPG, fault simulation, fault grading, and coverage analysis.
Support scan diagnosis and testability analysis.
Work with integration DFT teams to integrate IP-level DFT features into larger subsystems and SoCs.
Document DFT architecture, verification methodology, and test procedures.
Contribute to continuous improvement of mixed-signal DFT methodologies and best practices.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
7+ years of experience in DFT implementation for digital, mixed-signal, or semiconductor IP.
Strong understanding of DFT concepts including scan/scan insertion, ATPG, JTAG, test point insertion, scan diagnosis, fault simulation/fault grading, and test coverage analysis.
Experience with industry-standard DFT and simulation tools such as Synopsys DFT Compiler, TetraMax, Siemens Tessent, VCS, or Verdi.
Familiarity with RTL design and simulation, including Verilog and/or VHDL.
Understanding of analog or mixed-signal design and test concepts.
Experience with ATPG, fault grading, and coverage analysis for digital logic.
Strong analytical, debugging, problem-solving, and communication skills.

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